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fix on several equations

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Lieuwe Leene
2025-01-22 16:17:09 +01:00
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content/publications/2019/a-68-rmu-w-31-ks-s-fully-capacitive-noise-shaping-sar-adc-with-102-db-sndr.md
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@ -49,9 +49,10 @@ $$ QNP \approx \underbrace{\left( V^2_{DD} e^{-3\tau} + \frac{V^2_{DD}}{2^{2N}}
The expression in Eq. 2 parametrises the overall SAR resolution as N, the loop fillter order as M, and the number of time constants we allow the capacitive DAC to settle as τ \:in order to estimate QNP. This construction shows that settling and quantisation errors are shaped by the loop filter reducing the noise power by the term outside the brackets. Both in Fig. 3 and in the formulation we observe a strong dependency with regard to M as long as we provide sufficient settling time during SAR conversion. This result suggests that the noise-shaping feed-back must avoid driving the capacitive DAC with active amplifiers during successive-approximation to avoid slowing down the conversion speed or equivalently increasing the power requirement of each amplifier. We can also confirm here that the order of the loop filter does not need to be very high if the QNP needs to match the SNP.
$$ MNP \approx \underbrace{\left( \frac{\pi^2 2^{-2D}}{3 \cdot 2^K OSR^3} + \frac{\pi^{2E} 2^{-2K}}{(1+2E) OSR^{1+2E}} \right)}_{\text{DWA-MSB + MES-LSB DAC}} \frac{\sigma^2 V^2_{DD}}{3} $$
$$ MNP \approx \Delta^2 \underbrace{ \left( \frac{\pi^2 2^{-2D}}{3 \cdot 2^K OSR^3} + \frac{\pi^{2E} 2^{-2K}}{(1+2E) OSR^{1+2E}} \right) }_{\text{DWA-MSB + MES-LSB DAC}} $$
The MNP is evaluated in Eq. 3 with respect to the MES noise shaping order E, the number of bits D used to calibrate each capacitor in the MSB DAC in an idealised way. K represents the MSB DAC resolution in bits. Using a capacitor standard deviation \\(\sigma=0.5%\\) and K=4, the MNP of several configurations is shown in Fig. 4. The observation here is that for small OSR values the mismatch noise is typically dominated by the MSB DAC as the mismatch is not sufficiently shaped. It is relatively expensive to increase the number of elements in the MSB DAC since the scaling is linear and increasing the OSR diminishes the advantage of performing SAR. Instead we propose to calibrate the 15 capacitors in the MSB section as D will reduce the MNP more efficiently. The mismatch from the LSB section contains many more elements and is more effectively shaped using a second-order MES technique.
The MNP is evaluated in Eq. 3 with respect to the MES noise shaping order E, the number of bits D used to calibrate each capacitor in the MSB DAC in an idealised way. K represents the MSB DAC resolution in bits.
\\( \Delta^2 = \frac{\sigma^2 V^2_{DD}}{3}\\) represents the the capacitor mismatch power using a standard deviation \\(\sigma=0.5%\\) and K=4, the MNP of several configurations is shown in Fig. 4. The observation here is that for small OSR values the mismatch noise is typically dominated by the MSB DAC as the mismatch is not sufficiently shaped. It is relatively expensive to increase the number of elements in the MSB DAC since the scaling is linear and increasing the OSR diminishes the advantage of performing SAR. Instead we propose to calibrate the 15 capacitors in the MSB section as D will reduce the MNP more efficiently. The mismatch from the LSB section contains many more elements and is more effectively shaped using a second-order MES technique.
The above trends are used to optimise the FOM<sub>S<sub> in a similar fashion to [^3] by correlating hardware requirements with power and accuracy estimators for several configurations. Given an initial 18 bit target precision, we propose the following configuration: CT=50 pF, M=2,τ=5, K=5, D=4, E=2 with the OSR set to 16 to ease the decimation effort.
@ -117,7 +118,8 @@ This works presents a 17 bit Noise Shaping SAR ADC with reduced oversampling rat
# Refernces:
[^11]: S.Pavan, R.Schreier, and G.C. Temes, Understanding Delta-Sigma Data Converters.\hskip 1em plus 0.5em minus 0.4em
[^11]: S.Pavan, R.Schreier, and G.C. Temes, Understanding Delta-Sigma Data Converters.\hskip 1em plus 0.5em minus 0.4em
elax IEEE, 2017. [Online]: http://dx.doi.org/10.1002/9781119258308
[^12]: R.Schreier, J.Silva, J.Steensgaard, and G.C. Temes, ''Design-oriented estimation of thermal noise in switched-capacitor circuits,'' IEEE Trans. Circuits Syst. I, vol.52, no.11, pp. 2358--2368, Nov 2005. [Online]: http://dx.doi.org/10.1109/TCSI.2005.853909
[^10]: M.Aboudina and B.Razavi, ''A new DAC mismatch shaping technique for sigma–delta modulators,'' IEEE Trans. Circuits Syst. II, vol.57, no.12, pp. 966--970, Dec 2010. [Online]: http://dx.doi.org/10.1109/TCSII.2010.2083172
[^13]: J.Liu, G.Wen, and N.Sun, ''Second-order DAC MES for SAR ADCs,'' IET Elec. Letters, vol.53, no.24, pp. 1570--1572, 2017. [Online]: http://dx.doi.org/10.1049/el.2017.3138
@ -126,7 +128,8 @@ This works presents a 17 bit Noise Shaping SAR ADC with reduced oversampling rat
[^5]: A.AlMarashli, J.Anders, J.Becker, and M.Ortmanns, ''A nyquist rate SAR ADC employing incremental sigma delta DAC achieving peak SFDR=107 dB at 80 kS/s,'' IEEE J. Solid-State Circuits, vol.53, no.5, pp. 1493--1507, May 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2776299
[^4]: I.Jang etal., ''A 4.2 mW 10 MHz BW 74.4 dB SNDR continuous-time delta-sigma modulator with SAR-assisted digital-domain noise coupling,'' IEEE J. Solid-State Circuits, vol.53, no.4, pp. 1139--1148, April 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2778284
[^3]: L.B. Leene and T.G. Constandinou, ''A 0.016 mm sqrd 12 b $\Delta\Sigma$ SAR with 14 fJ/conv. for ultra low power biosensor arrays,'' IEEE Trans. Circuits Syst. I, vol.64, no.10, pp. 2655--2665, Oct 2017. [Online]: http://dx.doi.org/10.1109/TCSI.2017.2703580
[^3]: L.B. Leene and T.G. Constandinou, ''A 0.016 mm sqrd 12 b $\Delta\Sigma$ SAR with 14 fJ/conv. for ultra low power biosensor arrays,'' IEEE Trans. Circuits Syst. I, vol.64, no.10, pp. 2655--2665, Oct 2017. [Online]: http://dx.doi.org/10.1109/TCSI.2017.2703580
[^1]: Y.Chae, K.Souri, and K.A.A. Makinwa, ''A 6.3
mu W 20 bit incremental zoom-ADC with 6 ppm INL and 1 mu V offset,'' IEEE J. Solid-State Circuits, vol.48, no.12, pp. 3019--3027, Dec 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2278737
[^16]: S.Choi etal., ''An 84.6 dB-SNDR and 98.2 dB-SFDR residue-integrated SAR ADC for low-power sensor applications,'' IEEE J. Solid-State Circuits, vol.53, no.2, pp. 404--417, Feb 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2774287
[^2]: Y.Shu, L.Kuo, and T.Lo, ''An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55 nm CMOS,'' IEEE J. Solid-State Circuits, vol.51, no.12, pp. 2928--2940, Dec 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2592623
[^7]: J.A. Fredenburg and M.P. Flynn, ''A 90 MS/s 11 MHz bandwidth 62 dB SNDR noise-shaping SAR ADC,'' IEEE J. Solid-State Circuits, vol.47, no.12, pp. 2898--2904, Dec 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2217874