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title: "A 3rd order time domain delta sigma modulator with extended-phase detection"
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date: 2019-05-26T15:26:46+01:00
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draft: false
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toc: true
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type: posts
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math: true
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tags:
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- publication
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- CMOS
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- time-domain
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- instrumentation
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- circuit
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---
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Lieuwe B. Leene, Timothy G. Constandinou
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Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
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Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
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# 1 Abstract
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This paper presents a novel analogue to digital converter using an oscillator-based loop filter for high-dynamic range bio-sensing applications. This is the first third-order feed-forward ΔΣ modulator that strictly uses time domain integration for quantisation noise shaping. Furthermore we propose a new asynchronous extended-phase detection technique that increases the resolution of the 4 bit phase quantiser by another 5 bits to significantly improve both dynamic range and reduce the noise-shaping requirements. Preliminary simulation results show that this type of loop-filter can virtually prevent integrator saturation and achieves a peak 88 dB SNDR for kHz signals. The proposed system has been implemented using a 180 nm CMOS technology occupying 0.102 mm² and consumes 13.7 μ W of power to digitise the 15 kHz signal bandwidth using a 2 MHz sampling clock.
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# 2 Introduction
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Time and frequency based circuit techniques have received considerable interest in the recent years as a means to solve key challenges with integrating traditional analogue functionality into digital systems and take advantage of technology scaling [^1]. A feature in many of these developments relies on the ease by which an analogue voltage or current can be converted into time encoded signals using a simple digital ring oscillator that interfaces directly with standard logic elements. Generally time encoding implies that the analogue signal is represented by the time interval between digital events where we may use the frequency or phase difference to encode digital bit streams that are termed continuous time binary value (CTBV) signals.
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In ADCs specifically, frequency readout carefully counts the number of oscillations relative to a precise reference clock period[^2] while phase readout digitises the relative phase difference of two matched oscillators using an array of phase detectors [^3]. Seemingly the advantage of using a counter is that the dynamic range of the output is more flexible in the sense that the counter depth is adjustable to realise low or high precision readout. In contrast phase readout directly relates the number of delay stages to the number of quantisation levels which makes high resolution phase quantisation resource intensive in the analogue sense as these delay stages should be matched to avoid off-sets and spurious tones. The advantage of the later is that the output is unary encoded with inherent mismatch averaging properties that simplifies the feedback circuitry during digital to analogue conversion [^3]. That said, effort has been made to improve the phase digitisation in other ways but has been limited to single bit improvements [^4] or constrains the system to use synchronous operation [^5].
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Both readout techniques conventionally use synchronous circuits where the the timing information is latched which makes it difficult to further process signals in the time-domain without incurring quantisation noise. This can obstruct higher order noise shaping schemes although several solutions have already been proposed. For instance [^6] uses gated ring oscillators to realise a multi-stage noise shaping (MASH) topology and [^7] uses a higher-order analogue loop-filter to precede the oscillator to improve dynamic range. However both have yet to demonstrate the feasibility for high dynamic range data conversion and the analogue reliance limits the scalability of time-based operation in a way that is characteristically more useful for digital systems.
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More recent work considers the use of asynchronous readout that may be able to process signals entirely in the time-domain with reduced analogue complexity [^10][^8][^9]. This is promising as a variety of specialised loop filter topologies can not be realised using synchronous prior art. Moreover asynchronous digital systems can utilise a number of power-saving techniques such as signal-activity dependent processing [^11] or event driven control to reduce complexity and speed up operation [^12].
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{{< figure src="/images/iscas2019/td_sdm.svg" title="Figure 1: Block diagram of the third-order \\(\Sigma\Delta\\) instrumentation loop that uses time-domain integrator for noise shaping and an extended phase detector for high-resolution phase digitisation." width="500" >}}
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The system proposed here is shown in Fig. 1. This represents a third-order time domain ΔΣ modulator that uses capacitive feedback to linearise the digitisation process similar to [^9]. The primary contributions here aim to make improvements in the overall dynamic range of time based ADCs that use oversampled noise shaping. The negative feedback mechanism uses the error signal appearing on V<sub>x<sub> to feed a cascade of oscillator-based integrators inside the continuous-time (CT) loop filter H(s) that accumulates quantisation errors. This is followed by a phase detector that digitises the phase difference of a pseudo-differential oscillator. The distinction is that the loop filter uses a feed-forward topology with better noise-shaping dynamics than prior-art together with an extended-phase-detector (EPD) that asynchronously accounts for phase overflow without incurring distortion. Both of these innovations result in higher dynamic range by performing higher-order quantisation noise-shaping and resolving the baseline phase state with a total precision of 9 bits.
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This paper is organised as follows: Sec 3 will present the operating principle of oscillator-based ΔΣ modulation which guides the design for the proposed circuit described in Sec 4. Sec 5 will then demonstrate operating characteristics followed by Sec 7 that concludes this work.
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# 3 Oscillator Based \\(\Delta\Sigma\\) Conversion
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The design procedure of an oscillator based loop filter follows closely to that of conventional Gm-C based CT modulators as the anti-aliasing properties are retained with similar concerns for paracitic pole locations. The difference is that the small-signal currents are integrated by modulating the phase of a current controlled oscillator (CCO) instead of the voltage on a capacitor. This results in better output dynamic range as the oscillator based integrator can be full swing while Gm-C integrators usually have limited voltage-swing for intermediate stages to avoid non-linear behaviour of the proceeding stage. The large signal swing can be tolerated by using a digital current DAC inside intermediate integration stages that exhibit better linearity with a full-swing input. Arguably Gm-C integrators will exhibit better noise performance than current DACs which is why the first stage of the oscillator-based loop filter also uses a transconductor in sub-threshold operation to maximise noise efficiency of the overall system.
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$$ \phi (t) = \frac{f_{osc}}{I_{bias}} \int_{-\infty}^{t} i_{\Delta}(\tau) \: d\tau $$
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As a basis for oscillator based circuits, Equation 1 formulates the small-signal phase response φ(t) of a CCO in terms of the oscillation frequency f<sub>osc<sub>, the static bias current I<sub>bias<sub>, and the small-signal current input i\tss{Δ}[^13]. This simply tells us that the total amount of charge injected over time is accumulated and scaled by an integration factor. It is interesting to note that φ\: is dimensionless and represents a unit of time relative to the oscillator period. The signal driving this circuit is typically a transconductor or a current-steering DAC while the output φ\: can be read using a phase detector. Realising the loop filter uses the coefficients from an optimised CT-ΔΣ signal flow-graph for a 16 level quantiser and scales the transconductive elements according for a given set of oscillator frequencies.
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While this integration property is well established, it is important to point out that the oscillator output is inherently discretised in the value domain in a non-linear fashion before it is clocked. This process generates distortion tones at harmonics of the oscillation frequency and can be interpreted in terms of a pulse-width-modulation process. Consolidating the impact of these out-of-band spurs does not have an established framework for analysis for more complex oscillator configurations and extensively relies on simulator based validation. Some progress has been made for analysing open loop configurations[^14] that use frequency readout. In a closed loop environment however the oscillator frequency is not stationary but instead modulated by the signal and quantisation errors which is in turn dithered by the oscillation. The main concern here is down conversion of tones into the signal band although they are actively suppressed during closed loop operation. Choosing co-prime frequency ratios through scaled bias currents such as 2:3:13 as is used here is best way to avoid undesirable oscillator interaction.
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# 4 Circuit Implementation
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The proposed instrumentation circuit can be split into three sub-circuits and will be detailed following the sequence by which the analogue input signal is processed. The first stage is the capacitive feedback structure shown in Fig. 2. This figure shows the input analogue signal being chopped and coupled though C<sub>IN<sub> while a capacitor array also feeds the chopped digital codes which will allow the flicker noise of the input-transconductor to be modulated out of the signal-band. The digitised output Q\tss{9-5} uses binary weighting while the PWM signals \\(\Phi\\)\tss{1-15} use unary weighting and together they evaluate the quantisation error. The PWM encoded signals \\(\Phi\\)\tss{1-15} are used to compute the remaining binary least-significant codes for Q\tss{4-1} seen at the ADC output. The unary weighting averages out any mismatch components and will also assist in performing foreground calibration of binary weighted DAC by correlating the output derivative code transitions in Q\tss{9-5}[^15].
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{{< figure src="/images/iscas2019/td_cdac.svg" title="Figure 2: Capacitive feedback network that resolves the error signal when comparing the analogue input with the digitised output." width="500" >}}
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The error signal on the capacitive DAC can be directly applied to the loop filter used here. This structure is shown in Fig. 3. The first stage of the feed-forward topology is a high-power transconductor that boosts the noise efficiency factor of this structure and dominates the overall noise performance as it directly drives the first and last differential oscillator through the current biasing terminal. All oscillating taps of X\tss{1-2} are buffered and processed by a XOR phase-detector to evaluate the phase-state. This controls the current-output from each DAC and enables us to cascade several time-based integrators without inducing quantisation errors or requiring strict digital timing requirements. It is important to point out that in this case the extended phase-detection is only applied to the last integrator and thus the limited dynamic range of X\tss{1-2} can result in undesirable modulator dynamics for high-frequency inputs. For this reason the second-order integration component is derived by feeding the first integration state forward instead of the input component. In addition the last oscillator presents a \\(4\times\\) smaller integration load thereby inducing additional gain at the output. This strategy is also found in conventional CT-\\(\Delta\Sigma\\) modulators as its allows the integration constants for the first two stages to be reduced giving more headroom for signal dynamics.
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{{< figure src="/images/iscas2019/td_lf.svg" title="Figure 3: Configuration of the third-order modulator that uses a cascade of integrators with feed-forward compensation." width="500" >}}
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Fig. 4 shows the circuit implementation of the EPD that similarly monitors each oscillating tap of X<sub>3<sub>. Clearly the phase difference is also being detected using an XOR gate however this circuit also generates overflow and underflow events as UP and DN signals. These are generated by combining a double-edge sensitive flip-flop with time-domain processing to perform level detection[^13]. The principle of operation here is that the Q<sub>5<sub> will always track whichever oscillator in the differential structure is leading. When the XOR gate indicates a change has occurred, a phase-overflow will be triggered when the AND level detector is high otherwise the NOR level detector triggers a phase-underflow. These events trigger a counter that will increment or decrement accordingly thereby also correcting Q<sub>5<sub> and setting the overflow event indicators low. In high-speed scenarios a unary counter can also be used to generate thermometer codes directly at the cost of added circuit complexity to speed up code transitions in the feedback DAC.
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{{< figure src="/images/iscas2019/td_epd.svg" title="Figure 4: Schematic of the extended-phase read-out circuit that extracts both phase information and detects cycle over-flow for the N<sup>th<sup> section." width="500" >}}
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Fig. 5 shows the internal EPD signals during closed loop operation to clarify the circuit behaviour. This also shows that several phase-overflow events can be generated as X<sub>3<sub> undergoes cycle slipping. Note that only the digital output is clocked and the internal counter state generates Q asynchronously in response to these events. Due to quantisation noise modulation multiple UP/DN events can be generated but this configuration processes the digital control in a feed-forward manner allowing tight timing control to guarantee a glitch free output. This is done by using a 2 ns window during every rising clock edge that holds the UP/DN signal in a tri-state to prevent latching invalid counter codes.
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{{< figure src="/images/iscas2019/transition.svg" title="Figure 5: Transient waveform showing from top to bottom the pseudo differential oscillator output in volts, the phase-overflow trigger signal, and the two digital output codes \\(\Phi\\)1-15 & Q9-5." width="500" >}}
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Table 1: Performance summary and comparison with state of the art
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| Specification | This Work | [^9] | [^8] | [^7] | [^16] | [^4] | [^17] | [^3] |
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|----|----|----|----|----|----|----|----|----|
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| Year | 2018 | 2018 | 2018 | 2018 | 2017 | 2017 | 2015 | 2008 |
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| Tech.[nm] | 180 | 65 | 130 | 65 | 40 | 130 | 180 | 130 |
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| Supply[V] | 1.8/1.2 | 0.5 | 1.8 | - | 0.6 | 1.2 | 5/1.8 | 1.2 |
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| Power[W] | 13.6μ | 1.28μ | 0.56m | 51.8m | 3.3μ | 1.05m | 140μ | 40m |
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| Phase/Freq. | Φ-VCO | Φ-VCO | F-VCO | Φ-VCO | - | Φ-VCO | F-VCO | Φ-VCO |
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| Calibration | Yes | No | No | Yes | No | No | No | No |
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| NS-Order | 3 | 1 | 2 | 3 | 1 | 1 | 2 | 1 |
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| OSR | 64 | 128 | 500 | 15 | 83k | 313 | 64k | 100 |
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| BW[Hz] | 15.6k | 11k | 20k | 50M | 150 | 0.4M | 1.25 | 10M |
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| SNDR[dB] | 88 | 54 | 77 | 72 | 56 | 83 | 73 | 72 |
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| Area[mm²] | 0.102 | 0.006 | 0.04 | 0.35 | 0.015 | 0.13 | 0.36 | 0.01 |
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| FoM<sub>S<sub>[dB] | 178(^\star) | 153 | 152 | 162 | 133 | 169 | 97 | 156 |
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\\(^\star\\) Estimated based on simulation results where FoM<sub>S<sub> = SNDR + 10log<sub>10<sub>(BW/P).
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# 5 Simulation Results
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The time domain modulator presented here has been designed and validated using a commercially available 180 nm TSMC technology (1P6M HV BCD GEN II). The ADC core is configured to use a 1.8 V analogue supply to power the low noise transconductor as well as perform current biasing for each of the switched current DAC while using a 500 nA external reference current. The 1.8 V supply is also used as reference voltage when the digital codes are coupled onto V<sub>X<sub> using an array of level shifters since all the digital logic runs at 1.2 V to save power. A differential 2 kHz sinusoid at -3 dBFS (900 mVpp) is used during transient simulations to show preliminary performance characteristics. Fig. 6 shows one cycle where all three integrators are processing quantisation errors that are accumulated in X<sub>3<sub>. This also shows X<sub>3<sub> rapidly overflowing multiple times while triggering increments in the binary codes. At maximum input swing the speed is limited due to the slewing of X<sub>3<sub> but we do not expect such rapid signal dynamics for our application. Instead this extended dynamic range will capture drift and electrode offset components while the artefacts are typically 10 to 100 mV that the modulator can track at full-speed. The photo in Fig. 7 shows the floor plan as well as the layout of the fabricated prototype.
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{{< figure src="/images/iscas2019/sim_tran.svg" title="Figure 6: Simulation result transient behaviour of the time based integration where each phase state is asynchronously PWM encoded but only the output X<sub>3<sub> uses extended phase detection to allow overflow." width="500" >}}
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{{< figure src="/images/iscas2019/floor_plan.svg" title="Figure 7: Micro-photograph showing labelled blocks in relation to the schematics in Sec. 4." width="500" >}}
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The spectral characteristics are summarised in Fig. 8. We can observe that third-order noise shaping can be achieved but some of the oscillator spurs are still present in high-frequency bands. However the components close to the signal band are significantly suppressed. The oscillator frequencies have also been annotated where X1 is around 78 kHz, X2 is around 117 kHz, and X3 is around 507 kHz. The chopper tones are still present outside the signal band since no off-set cancellation is performed which will be considered at a later point. The performance metrics are compared with other time based data converters in Table 1. While the figure of merit (FOM) seems to favour this work, the calibration mechanism is not yet integrated and measurements will need to confirm the these figures using a prototype that is currently in the process of being fabricated.
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{{< figure src="/images/iscas2019/sim_thd.svg" title="Figure 8: Simulation result showing the noise-shaped output spectrum from a -3 dBFS input sinusoid at 2 kHz." width="500" >}}
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# 6 Acknowledgement
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This work was supported by the UK Engineering and Physical Sciences Research Council (EPSRC) grants EP/M020975/1 & EP/R024642/1.
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# 7 Conclusion
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We have presented the implementation and operation of a third-order ΣΔ ADC that uses an oscillator based loop filter with extended phase detection. As a result this work shows a significant improvement in precision over prior-art that strictly uses time-based signal processing. While the preliminary results show the performance for an analogue 180 nm CMOS technology, the digital operation of these circuits will enable these ideas to easily be adopted in a modern digital process or target high-speed applications. More importantly this work demonstrates that asynchronous time domain systems can be configured to achieve well over 80 dB dynamic range and realise intergrators that will not induce distortion due to saturation or phase-overflow.
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# Refernces:
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[^17]: P.Prabha etal., ''A highly digital VCO-based ADC architecture for current sensing applications,'' IEEE J. Solid-State Circuits, vol.50, no.8, pp. 1785--1795, Aug 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2414428
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[^7]: S.Dey, K.Reddy, K.Mayaram, and T.S. Fiez, ''A 50 MHz BW 76.1 dB DR two-stage continuous-time delta-sigma modulator with VCO quantizer nonlinearity cancellation,'' IEEE J. Solid-State Circuits, vol.53, no.3, pp. 799--813, March 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2777455
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[^2]: R.Naiknaware, H.Tang, and T.S. Fiez, ''Time-referenced single-path multi-bit $\Delta \Sigma$ ADC using a VCO-based quantizer,'' IEEE Trans. Circuits Syst. II, vol.47, no.7, pp. 596--602, July 2000. [Online]: http://dx.doi.org/10.1109/82.850418
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[^3]: M.Z. Straayer and M.H. Perrott, ''A 12 bit, 10 MHz bandwidth, continuous-time $\Sigma\Delta$ ADC with a 5 bit, 950 MS/s VCO-based quantizer,'' IEEE J. Solid-State Circuits, vol.43, no.4, pp. 805--814, April 2008. [Online]: http://dx.doi.org/10.1109/JSSC.2008.917500
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[^16]: R.Mohan etal., ''A 0.6 V, 0.015 mm sqrd, time-based ECG readout for ambulatory applications in 40 nm CMOS,'' IEEE J. Solid-State Circuits, vol.52, no.1, pp. 298--308, Jan 2017. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2615320
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[^10]: S.Ziabakhsh, G.Gagnon, and G.W. Roberts, ''A time-mode LDI-based resonator for a band-pass $\Delta\Sigma$ TDC,'' Aug 2017, pp. 1296--1299. [Online]: http://dx.doi.org/10.1109/MWSCAS.2017.8053168
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[^8]: F.Cardes etal., ''0.04 mm sqrd 103 dB-A dynamic range second-order VCO-based audio $\Sigma\Delta$ ADC in 0.13 $\mu$m CMOS,'' IEEE J. Solid-State Circuits, vol.53, no.6, pp. 1731--1742, June 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2018.2799938
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[^9]: L.B. Leene and T.G. Constandinou, ''A 0.006 mm sqrd 1.2 $\mu$W analog-to-time converter for asynchronous bio-sensors,'' IEEE J. Solid-State Circuits, vol.53, no.9, pp. 2604--2613, Sept 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2018.2850918
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[^1]: G.W. Roberts and M.Ali-Bakhshian, ''A brief introduction to time-to-digital and digital-to-time converters,'' IEEE Trans. Circuits Syst. II, vol.57, no.3, pp. 153--157, March 2010. [Online]: http://dx.doi.org/10.1109/TCSII.2010.2043382
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[^13]: L.B. Leene and T.G. Constandinou, ''Time domain processing techniques using ring oscillator-based filter structures,'' IEEE Trans. Circuits Syst. I, vol.64, no.12, pp. 3003--3012, Dec 2017. [Online]: http://dx.doi.org/10.1109/TCSI.2017.2715885
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[^14]: E.Gutierrez, L.Hernandez, F.Cardes, and P.Rombouts, ''A pulse frequency modulation interpretation of VCOs enabling VCO-ADC architectures with extended noise shaping,'' IEEE Trans. Circuits Syst. I, vol.65, no.2, pp. 444--457, Feb 2018. [Online]: http://dx.doi.org/10.1109/TCSI.2017.2737830
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[^12]: J.Beaumont, A.Mokhov, D.Sokolov, and A.Yakovlev, ''High-level asynchronous concepts at the interface between analog and digital worlds,'' IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.37, no.1, pp. 61--74, Jan 2018. [Online]: http://dx.doi.org/10.1109/TCAD.2017.2748002
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[^11]: B.Schell and Y.Tsividis, ''A continuous-time ADC/DSP/DAC system with no clock and with activity-dependent power dissipation,'' IEEE J. Solid-State Circuits, vol.43, no.11, pp. 2472--2481, Nov 2008. [Online]: http://dx.doi.org/10.1109/JSSC.2008.2005456
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[^15]: L.B. Leene and T.G. Constandinou, ''A 0.016 mm sqrd12 b $\Delta \Sigma$ SAR with 14 fJ/conv. for ultra low power biosensor arrays,'' IEEE Trans. Circuits Syst. I, vol.64, no.10, pp. 2655--2665, Oct 2017. [Online]: http://dx.doi.org/10.1109/TCSI.2017.2703580
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[^5]: W.Jiang etal., ''A ±50 mV linear-input-range VCO-based neural-recording front-end with digital nonlinearity correction,'' IEEE J. Solid-State Circuits, vol.52, no.1, pp. 173--184, Jan 2017. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2624989
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[^4]: S.Li, A.Mukherjee, and N.Sun, ''A 174.3 dB FoM VCO-based CT $\Delta \Sigma$ modulator with a fully-digital phase extended quantizer and tri-level resistor DAC in 130 nm CMOS,'' IEEE J. Solid-State Circuits, vol.52, no.7, pp. 1940--1952, July 2017. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2693244
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[^6]: W.Yu, J.Kim, K.Kim, and S.Cho, ''A time-domain high-order MASH $\Delta\Sigma$ adc using voltage-controlled gated-ring oscillator,'' IEEE Trans. Circuits Syst. I, vol.60, no.4, pp. 856--866, April 2013. [Online]: http://dx.doi.org/10.1109/TCSI.2012.2209298
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@ -0,0 +1,135 @@
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---
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title: "A 68 μW 31 kS/s fully-capacitive noise-shaping SAR ADC with 102 dB SNDR"
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date: 2019-05-26T15:26:46+01:00
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draft: false
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toc: true
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math: true
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||||
type: posts
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tags:
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- publication
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- CMOS
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- data-converter
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- instrumentation
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- circuit
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---
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Lieuwe B. Leene, Timothy G. Constandinou
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Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
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Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
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# 1 Abstract
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This paper presents a 17 bit analogue-to-digital converter that incorporates mismatch and quantisation noise-shaping techniques into an energy-saving 10 bit successive approximation quantiser to increase the dynamic range by another 42 dB. We propose a novel fully-capacitive topology which allows for high-speed asynchronous conversion together with a background calibration scheme to reduce the oversampling requirement by 10\\(\times\\) compared to prior-art. A 0.18μ m CMOS technology is used to demonstrate preliminary simulation results together with analytic measures that optimise parameter and topology selection. The proposed system is able to achieve a FoM<sub>S<sub> of 183 dB for a maximum signal bandwidth of 15.6 kHz while dissipating 68 μ W from a 1.8 V supply. A peak SNDR of 102 dB is demonstrated for this rate with a 0.201 mm² \:area requirement.
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# 2 Introduction
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Analogue-to-digital converter (ADC) efficiency remains to be the highlight for many current developments in both industry and academia. It used to be the case that oversampling converters (ΔΣ ADCs) and successive-approximation register converters (SAR ADCs) found separate application domains where this factor peaks. State-of-the-art ADCs however have mixed these two digitisation techniques to improve performance beyond a 170 dB Schreier Figure-of-Merit (FoM<sub>S<sub>)[^5][^4][^3][^1][^2]. This trend is in-part driven by the growing bio-metric and bio-medical electronics market that necessitates low-power high dynamic-range signal acquisition as many phenomena of interest exhibit signal dynamics with several orders of magnitude in variation. For example a peripheral neuro-modulation device with digitally assisted artifact rejection[^6] requires over \\(>\\)100 dB of dynamic range to detect micro-volt level sensory neuron activity in the presence of large mili-volt level interference from stimulation or motor-unit activity which is the application of interest that motivated this work.
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The emerging ADC topologies for bio-sensors use multi-stage noise shaping or pipe-lined operation where multiple quantisers are integrated together and the quantisation error of the first quantiser is either resolved by another quantiser after amplification or may be used directly with an alternate feedback mechanism to similarly resolve additional bits. The noise-shaping SAR (NS-SAR) [^2][^7] however adopts a different approach by sampling and converting the input multiple times while simultaneously employing multiple feedback mechanisms that up-modulate any conversion errors out of the signal bandwidth. In this way the signal can be resolved with much finer precision once the output is decimated and the out-of-band frequency components are filtered out.
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{{< figure src="/images/iscas2019/sar_sys.svg" title="Figure 1: Block diagram of the proposed high-resolution data converter showing the SAR digital controller applying feedback through 3 separate capacitor arrays and is augmented by the switched-capacitor loop filter H(z\tps{-1})." width="500" >}}
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Here we present a novel fully-capacitive NS-SAR topology using active higher-order noise shaping that achieves state-of-the-art efficiency for high resolution signal acquisition. The proposed configuration is shown in Fig. 1. This figure summarises which signals are processed by each block in a closed-loop fashion to resolve the sampled analogue input signal V<sub>IN<sub>. The main data-conversion mechanism is based on the conventional SAR controller that uses the comparator decisions K to successively set the MSB and LSB bits[^8]. However to augment this operation two separate noise-shaping mechanisms are added; one for quantisation noise, H(z\tps{-1}), and another for mismatch noise by means of data-weighted averaging (DWA) together with mismatch-error shaping techniques (MES).
|
||||
|
||||
The NS-SAR approach is advantageous because the first several bits can be resolved rapidly using SAR and the remaining bits are resolved using ΔΣ modulation over several samples with reduced oversampling-ratio (OSR) to yield a significant overall improvement in conversion efficiency. Reusing the sampling mechanism of the SAR allows the quantisation residue left on V<sub>DAC<sub> to be directly integrated by the loop filter H(z\tps{-1}) that off-sets future conversions and shapes the quantisation noise as 1/(1+H(z\tps{-1})). The main drawback here in comparison to high-resolution \rDS\: modulators is that, while the conversion is faster, the mismatch in the high-resolution DAC must be carefully mitigated. This is where the DWA[^9] and MES[^10] are introduced to eliminate mismatch errors. DWA manipulates the selection of elements used within the MSB capacitive DAC such that the capacitor mismatch is not only decorrelated from the input but is also shaped with a (1-z\tps{-1}) characteristic. The MES module in the LSB section directly off-sets the sampled input using past conversion results to realise a FIR feedback structure such as (1-z\tps{-1}) or (1-2z\tps{-1}+z\tps{-2}) high-pass characteristics to minimise signal-band noise components.
|
||||
|
||||
The rest of this paper is organised as follows; Sec. 3 will relate the main design parameters to conversion precision in relation to primary noise sources. Once these are established the circuit implementation is presented in Sec. 4 together with simulation results in Sec. 5 and Sec. 7 will then conclude this work.
|
||||
|
||||
# 3 NS-SAR Design
|
||||
|
||||
Comparing with other data-converters, the NS-SAR topology is quite complex with a large number of design parameters that need to be optimised for efficient operation. Below, several of these parameters are discussed in relation to the ADC precision explaining the proposed configuration. Following the single-ended configuration shown in Fig. 1, we will estimate the expected sampling noise power (SNP), quantisation noise power (QNP), and mismatch noise power (MNP) for the signal bandwidth of fs/(2 OSR) where fs is the sampling speed. This formulation is purposely presented in brief since it based on established theory from [^11] but it does well to illustrate several trade-off considerations quantitatively when configuring this topology for a particular precision requirement.
|
||||
|
||||
$$ SNP \approx \frac{kT}{C_T} \cdot \frac{2.4}{OSR} $$
|
||||
|
||||
The expression in Eq. 1 should be a familiar representation for evaluating the input-referred sampling noise associated with a switched-capacitor integrator. In particular, this corresponds to the input being sampled with a total capacitive value of C<sub>T<sub> using kT as the Boltzman temperature factor. The second term simply arises from averaging the input over OSR cycles together with a correction factor of 2.4 due to the integrator topology in H(z\tps{-1})[^12]. Fig. 2 shows the estimated resolution for several capacitor values assuming we use an input sinusoid with maximum signal power (SP) given a 1.8 V ADC reference voltage as V<sub>DD<sub>. Inevitably, achieving high resolution implies a large sampling capacitance or a large oversampling ratio. Typically the former is preferred because increasing the capacitive load also decreases the mismatch power from the capacitive DACs.
|
||||
|
||||
$$ QNP \approx \underbrace{\left( V^2_{DD} e^{-3\tau} + \frac{V^2_{DD}}{2^{2N}} \right)}_{\text{SAR settling + quantisation }\epsilon} \cdot \frac{\pi^{2M}}{12 (1+2M) OSR^{1+2M}} $$
|
||||
|
||||
The expression in Eq. 2 parametrises the overall SAR resolution as N, the loop fillter order as M, and the number of time constants we allow the capacitive DAC to settle as τ \:in order to estimate QNP. This construction shows that settling and quantisation errors are shaped by the loop filter reducing the noise power by the term outside the brackets. Both in Fig. 3 and in the formulation we observe a strong dependency with regard to M as long as we provide sufficient settling time during SAR conversion. This result suggests that the noise-shaping feed-back must avoid driving the capacitive DAC with active amplifiers during successive-approximation to avoid slowing down the conversion speed or equivalently increasing the power requirement of each amplifier. We can also confirm here that the order of the loop filter does not need to be very high if the QNP needs to match the SNP.
|
||||
|
||||
$$ MNP \approx \underbrace{\left( \frac{\pi^2 2^{-2D}}{3 \cdot 2^K OSR^3} + \frac{\pi^{2E} 2^{-2K}}{(1+2E) OSR^{1+2E}} \right)}_{\text{DWA-MSB + MES-LSB DAC}} \frac{\sigma^2 V^2_{DD}}{3} $$
|
||||
|
||||
The MNP is evaluated in Eq. 3 with respect to the MES noise shaping order E, the number of bits D used to calibrate each capacitor in the MSB DAC in an idealised way. K represents the MSB DAC resolution in bits. Using a capacitor standard deviation \\(\sigma=0.5%\\) and K=4, the MNP of several configurations is shown in Fig. 4. The observation here is that for small OSR values the mismatch noise is typically dominated by the MSB DAC as the mismatch is not sufficiently shaped. It is relatively expensive to increase the number of elements in the MSB DAC since the scaling is linear and increasing the OSR diminishes the advantage of performing SAR. Instead we propose to calibrate the 15 capacitors in the MSB section as D will reduce the MNP more efficiently. The mismatch from the LSB section contains many more elements and is more effectively shaped using a second-order MES technique.
|
||||
|
||||
The above trends are used to optimise the FOM<sub>S<sub> in a similar fashion to [^3] by correlating hardware requirements with power and accuracy estimators for several configurations. Given an initial 18 bit target precision, we propose the following configuration: CT=50 pF, M=2,τ=5, K=5, D=4, E=2 with the OSR set to 16 to ease the decimation effort.
|
||||
|
||||
{{< figure src="/images/iscas2019/osr_snp.svg" title="Figure 2: ADC precision as a function of oversampling ratio with respect to SNP while varying sampling capacitance C<sub>T<sub>." width="500" >}}
|
||||
|
||||
{{< figure src="/images/iscas2019/osr_qnp.svg" title="Figure 3: ADC precision as a function of oversampling ratio with respect to QNP while varying settling times \\(\tau\\) and noise-shaping order M." width="500" >}}
|
||||
|
||||
{{< figure src="/images/iscas2019/osr_mnp.svg" title="Figure 4: ADC precision as a function of oversampling ratio with respect to MNP while varying calibration D and mismatch-shaping order E." width="500" >}}
|
||||
|
||||
# 4 Circuit Implementation
|
||||
|
||||
The analogue part of the ADC implementation is shown in Fig. 5. Note that the implemented ADC uses an equivalent fully-differential configuration to gain extra input-dynamic range as well as digital noise suppression. This realisation is entirely based on manipulating the capacitive DAC and enables low-power operation for varying sampling rates. A second distinguishing feature of the proposed topology is that the comparator only requires one input terminal opposed to two seen in prior-art [^2][^7] which leads to better linearity and noise performance. In addition the input is bottom plate sampled such that sensitivity to parasitic capacitance and comparator non-linearity is considerably reduced. This figure also shows three capacitor arrays where the DAC<sub>M<sub> section corresponds to the DWA modulated MSBs and the DAC\tss{L1/L2} section represents the MES modulated LSBs being fed back from the SAR controller. Implementing the second-order MES noise-shaping uses the ping-pong configuration from [^13].
|
||||
|
||||
{{< figure src="/images/iscas2019/sar_cdac.svg" title="Figure 5: Implementation of the capacitor network used to perform signal conversion using the bottom sampled capacitor arrays DAC<sub>M<sub> for the DWA bits and DAC<sub>L1<sub> & DAC<sub>L2<sub> for the MES bits. The loop filter is also shown where A<sub>1<sub> amplifies the quantisation residue that is then integrated by A<sub>2<sub> & A<sub>3<sub> for noise-shaping." width="500" >}}
|
||||
|
||||
Three switched-capacitor amplifiers are used to realise a second-order cascaded-feed-forward-integrator (CFFI) loop filter topology where the first stage provides auto-zeroing as well as signal amplification by \\(C_T/C_1\approx30\\). This design uses an asynchronous SAR conversion process [^14] which is why there are only 3 phases in the switched capacitor circuit; the sampling phase (SMP), the successive approximation phase (SAR), and the quantisation filtering phase (QNF). The SAR only takes 100 ns and the FSM immediately initiates the QNF phase reducing the input clock to twice the sampling rate. The three phases operate as follows:
|
||||
|
||||
\begin{enumerate}
|
||||
\item[**SMP**] First A<sub>1<sub> actively samples its offset on the top plate while bottom plate samples V<sub>IN<sub> on DAC<sub>M<sub> together with the MES code on DAC\tss{L1/L2}. A\tss{2/3} are simultaneously integrating quantisation errors and sampling the result V\tss{X2/X3} with respect to V<sub>DAC<sub> on C<sub>6<sub> and C<sub>7<sub>.
|
||||
\item[**SAR**] V<sub>DAC<sub> then converges to virtual ground by switching the input to DAC\tss{M/L1/L2} while quantisation errors from prior conversions are removed by grounding the bottom plate of C\tss{6/7}. This also disconnects A\tss{1/2/3} from V<sub>DAC<sub>.
|
||||
\item[**QNF**] Finally DAC\tss{M/L1/L2} is held and the resulting quantisation residue left on V<sub>DAC<sub> is amplified by A{1} on V<sub>X1<sub>. C\tss{2/4} samples the voltages V\tss{X1/X2} which are used to integrate during the following SMP phase.
|
||||
\end{enumerate}
|
||||
|
||||
This configuration scales well for varying loop filter structures as 80% of the power is dissipated by A<sub>1<sub> and the total sampling noise is dominated by C<sub>T<sub>. The comparator uses a conventional strong-arm topology that is carefully designed to minimise off-set since this off-set will be seen at the output of A<sub>3<sub> after amplification which can diminish the output-swing. Conversely the noise and distortion characteristics of the analogue filtering chain is proportionally reduced when the signal is fed back onto the capacitor array during sampling as the attenuation ratio \\(C_{6-7}/C_T\\) inverts the amplification ratio with good matching.
|
||||
|
||||
The MSB DAC calibration mechanism is uses a digital shuffling technique to identify mismatch by switching out different sets of capacitors that will only incur voltage fluctuation on V<sub>DAC<sub> in the presence of mismatch[^15]. These errors are then amplified by A<sub>1<sub> after the SAR & QNF process and digitally tunes each MSB capacitor using a capacitive sub-DAC. The sign of each shuffling result is accumulated to adjust the the 15 calibration codes thereby eliminating the mismatch in the MSB DAC. This process can be performed in the background without requirements on the input signal because DWA randomises the capacitor selection mechanism during shuffling.
|
||||
|
||||
Table 1: Performance summary and comparison with state of the art
|
||||
| Spec. | This Work | [^16] | [^15] | [^4] | [^5] | [^3] | [^7] | [^2] |
|
||||
|----|----|----|----|----|----|----|----|----|
|
||||
| Year | 2018 | 2018 | 2018 | 2018 | 2018 | 2017 | 2016 | 2012 |
|
||||
| Tech.[nm] | 180 | 180 | 180 | 28 | 40 | 180 | 55 | 65 |
|
||||
| Supply[V] | 1.8 | 1.8 | 1.8/5 | 1.1/1.2 | 2.5/1.1 | 1.2 | 1.2 | 1.2 |
|
||||
| Power[W] | 68μ | 7.93μ | 12.9m | 4.2m | 140μ | 5.16μ | 15.7μ | 806μ |
|
||||
| Topology | NS-SAR | \rDS-SAR | SAR | CT-\rDS | \rDS-SAR | \rDS-SAR | NS-SAR | NS-SAR |
|
||||
| DAC Res.[b] | 10 | 9 | 20 | 4 | 7 | 8 | 12 | 8 |
|
||||
| NS-Order | 2(^\dagger) | 1 | 0 | 2(^\dagger) | 3 | 2 | 1(^\dagger) | 1(^\dagger) |
|
||||
| OSR | 16 | 256 | 1 | 16 | 12 | 24 | 256 | 4 |
|
||||
| BW[Hz] | 15.6k | 1k | 500k | 10M | 40k | 100k | 4k | 11M |
|
||||
| SNDR[dB] | 102 | 85 | 102 | 94 | 84 | 67 | 96.1 | 62 |
|
||||
| Area[mm²] | 0.201 | 0.68 | 4 | 0.1 | 0.07 | 0.02 | 0.07 | 0.03 |
|
||||
| FoM<sub>S<sub>[dB] | 183(^\star) | 166 | 176 | 168 | 169 | 170 | 180 | 164 |
|
||||
|
||||
\\(^\star\\) Estimated based on post-layout simulation results where FoM<sub>S<sub> = SNDR + 10log<sub>10<sub>(BW/P). \\(^\dagger\\) FIR & digital noise-coupling poles excluded.
|
||||
|
||||
# 5 Simulation Results
|
||||
|
||||
The proposed NS-SAR has been designed and validated using a commercially available 180 nm TSMC technology (1P6M HV BCD GEN II). All sub-circuits have been integrated with reconfigurable ΔΣ, DWA, MES, and calibration modes to fully characterise post-silicon performance that will confirm the evaluation in Sec. 3. This circuit uses an analogue and digital supply at 1.8 V, a 1 μ A current reference to bias A\tss{1-3}, and a 0.9 V common-mode reference for V<sub>CM<sub>-based capacitor switching. Preliminary post-layout simulation results are shown in Fig. 6. This demonstrates the ADC can resolve 17 bits of precision without distortion while using an external clock of 1 MHz where one cycle is used to sample the input and one cycle is used for conversion plus quantisation noise shaping and another cycle is optionally used for background calibration. The last phase can be skipped if the MSB capacitors are already tuned to speed-up signal conversion to 31.25 kS/s since temperature and voltage variations over time during normal operation will typically not corrupt the calibrated capacitor characteristics.
|
||||
|
||||
{{< figure src="/images/iscas2019/sar_sim_thd.svg" title="Figure 6: Post-layout simulation result showing the noise-shaped output spectrum from a -3 dBFS input sinusoid at 6.5 kHz." width="500" >}}
|
||||
|
||||
{{< figure src="/images/iscas2019/sar_floor_plan.svg" title="Figure 7: ADC micro-photograph showing labelled blocks in relation to Fig 1 where the MES and DWA circuitry is included in the main digital core. Decoupling capacitors are placed over active circuitry or underneath active mim-caps." width="500" >}}
|
||||
|
||||
The layout for this ADC is shown in Fig. 7. A large majority of silicon area is dedicated towards the MSB capacitive array as the sampling noise must be suppressed. The switched capacitor integrator can be relatively small because the internal loop-filter gain reduces its sampling noise. The digital core takes up a considerable amount of area and power budget primarily as a result of using a 180 nm CMOS technology where more advanced technologies may lead to further improvements if the 1.8 V rating can be maintained. Each MSB capacitor is trimmed using a 8 bit sub-DAC that tunes about 5% of the 1.7 pF unit capacitance which accommodates well over 3σ of the expected capacitor mismatch as well as wafer level variations that may not be captured by the typical mismatch model. The performance measures for the proposed ADC are shown in Table 1. Again we highlight the fact that while all these works have highly optimised power budgets, this topology is able to achieve over 100 dB SNDR with a 10\\(\times\\) lower oversampling ratio than prior art for this level precision. While this does imply a marginally increased area requirement, the peak efficiency can be achieved over a greater span of sampling frequencies. Note that this particular TSMC process kit does not allow post-layout Monte-Carlo so the calibration will be validated using post-silicon results.
|
||||
|
||||
# 6 Acknowledgement
|
||||
|
||||
This work was supported by the UK Engineering and Physical Sciences Research Council (EPSRC) grants EP/M020975/1 & EP/R024642/1.
|
||||
|
||||
# 7 Conclusion
|
||||
|
||||
This works presents a 17 bit Noise Shaping SAR ADC with reduced oversampling ratio and a purely capacitive implementation which enables in state-of-the-art conversion efficiency over a large range of sampling frequencies. In comparison with conventional over-sampling ADCs simulation results suggest this NS-SAR is able to achieve 102 dB SNDR with substantially lower noise-shaping requirements with comparable or reduced circuit complexity while achieving better power efficiency. We also demonstrated a high-level parameter selection methodology that is used to optimise the FoM<sub>S<sub> and identify the factors limiting ADC precision.
|
||||
|
||||
# Refernces:
|
||||
|
||||
[^11]: S.Pavan, R.Schreier, and G.C. Temes, Understanding Delta-Sigma Data Converters.\hskip 1em plus 0.5em minus 0.4em
|
||||
elax IEEE, 2017. [Online]: http://dx.doi.org/10.1002/9781119258308
|
||||
[^12]: R.Schreier, J.Silva, J.Steensgaard, and G.C. Temes, ''Design-oriented estimation of thermal noise in switched-capacitor circuits,'' IEEE Trans. Circuits Syst. I, vol.52, no.11, pp. 2358--2368, Nov 2005. [Online]: http://dx.doi.org/10.1109/TCSI.2005.853909
|
||||
[^10]: M.Aboudina and B.Razavi, ''A new DAC mismatch shaping technique for sigma–delta modulators,'' IEEE Trans. Circuits Syst. II, vol.57, no.12, pp. 966--970, Dec 2010. [Online]: http://dx.doi.org/10.1109/TCSII.2010.2083172
|
||||
[^13]: J.Liu, G.Wen, and N.Sun, ''Second-order DAC MES for SAR ADCs,'' IET Elec. Letters, vol.53, no.24, pp. 1570--1572, 2017. [Online]: http://dx.doi.org/10.1049/el.2017.3138
|
||||
[^9]: B.H. Leung and S.Sutarja, ''Multibit sigma - delta A/D converter incorporating a novel class of dynamic element matching techniques,'' IEEE Trans. Circuits Syst. II, vol.39, no.1, pp. 35--51, Jan 1992. [Online]: http://dx.doi.org/10.1109/82.204108
|
||||
[^8]: B.P. Ginsburg and A.P. Chandrakasan, ''500 MS/s 5 bit ADC in 65 nm CMOS with split capacitor array DAC,'' IEEE J. Solid-State Circuits, vol.42, no.4, pp. 739--747, April 2007. [Online]: http://dx.doi.org/10.1109/JSSC.2007.892169
|
||||
[^5]: A.AlMarashli, J.Anders, J.Becker, and M.Ortmanns, ''A nyquist rate SAR ADC employing incremental sigma delta DAC achieving peak SFDR=107 dB at 80 kS/s,'' IEEE J. Solid-State Circuits, vol.53, no.5, pp. 1493--1507, May 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2776299
|
||||
[^4]: I.Jang etal., ''A 4.2 mW 10 MHz BW 74.4 dB SNDR continuous-time delta-sigma modulator with SAR-assisted digital-domain noise coupling,'' IEEE J. Solid-State Circuits, vol.53, no.4, pp. 1139--1148, April 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2778284
|
||||
[^3]: L.B. Leene and T.G. Constandinou, ''A 0.016 mm sqrd 12 b $\Delta\Sigma$ SAR with 14 fJ/conv. for ultra low power biosensor arrays,'' IEEE Trans. Circuits Syst. I, vol.64, no.10, pp. 2655--2665, Oct 2017. [Online]: http://dx.doi.org/10.1109/TCSI.2017.2703580
|
||||
[^1]: Y.Chae, K.Souri, and K.A.A. Makinwa, ''A 6.3
|
||||
mu W 20 bit incremental zoom-ADC with 6 ppm INL and 1 mu V offset,'' IEEE J. Solid-State Circuits, vol.48, no.12, pp. 3019--3027, Dec 2013. [Online]: http://dx.doi.org/10.1109/JSSC.2013.2278737
|
||||
[^16]: S.Choi etal., ''An 84.6 dB-SNDR and 98.2 dB-SFDR residue-integrated SAR ADC for low-power sensor applications,'' IEEE J. Solid-State Circuits, vol.53, no.2, pp. 404--417, Feb 2018. [Online]: http://dx.doi.org/10.1109/JSSC.2017.2774287
|
||||
[^2]: Y.Shu, L.Kuo, and T.Lo, ''An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55 nm CMOS,'' IEEE J. Solid-State Circuits, vol.51, no.12, pp. 2928--2940, Dec 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2592623
|
||||
[^7]: J.A. Fredenburg and M.P. Flynn, ''A 90 MS/s 11 MHz bandwidth 62 dB SNDR noise-shaping SAR ADC,'' IEEE J. Solid-State Circuits, vol.47, no.12, pp. 2898--2904, Dec 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2217874
|
||||
[^6]: A.E. Mendrela etal., ''A bidirectional neural interface circuit with active stimulation artifact cancellation and cross-channel common-mode noise suppression,'' IEEE J. Solid-State Circuits, vol.51, no.4, pp. 955--965, April 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2506651
|
||||
@ -0,0 +1,14 @@
|
||||
---
|
||||
title: "An Oscillator Based Potentiostat with Switch-Cap Feedback for Current Sensing Applications"
|
||||
date: 2019-05-26T15:26:46+01:00
|
||||
draft: true
|
||||
toc: true
|
||||
type: posts
|
||||
math: true
|
||||
tags:
|
||||
- publication
|
||||
- CMOS
|
||||
- data-converter
|
||||
- instrumentation
|
||||
- circuit
|
||||
---
|
||||
@ -0,0 +1,13 @@
|
||||
---
|
||||
title: "Towards a distributed, chronically-implantable neural interface"
|
||||
date: 2019-03-20T15:26:46+01:00
|
||||
draft: true
|
||||
toc: true
|
||||
type: posts
|
||||
math: true
|
||||
tags:
|
||||
- chapter
|
||||
- packaging
|
||||
- biomedical
|
||||
- instrumentation
|
||||
---
|
||||
Reference in New Issue
Block a user