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---
title: "A 0.006 mm2 1.2 uW Analog-to-Time Converter for Asynchronous Bio-Sensors"
date: 2018-07-23T15:26:46+01:00
draft: false
toc: true
type: posts
math: true
tags:
- publication
- CMOS
- circuits
- data-converter
- biomedical
---
Lieuwe B. Leene, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
This work presents a low-power analogue-to-time converter (ATC) for integrated bio-sensors. The proposed circuit facilitates the direct conversion of electrode biopotential recordings into time-encoded digital pulses with high efficiency without prior signal amplification. This approach reduces the circuit complexity for multi-channel instrumentation systems and allows asynchronous digital control to maximise the potential power savings during sensor inactivity. A prototype fabricated using a 65 nm CMOS technology is demonstrated with measured characteristics. Experimental results show an input-referred noise figure of 3.8 μ V<sub>rms<sub> for a 11 kHz signal bandwidth while dissipating 1.2 μ W from a 0.5 V supply and occupying 60\\(\times\\)80 μ m² silicon area. This compact configuration is enabled by the proposed asynchronous readout that shapes the mismatch components arising from the multi-bit quantiser and the use of capacitive feedback.
# 2 Introduction
The current trend in sensor systems is to integrate many analogue sensors together with larger digital systems to provide smart data collection for miniaturised wearables or low cost system-in-package (SiP) electronics [^2][^1]. The digital oriented design flow of these systems compels designers to look for sensor interfaces that accommodate the trends in CMOS technology scaling and smaller supply voltages for digital power reduction. For this reason many data converters and sensing circuits have utilised voltage controlled oscillators (VCO) to convert analogue signals into a periodic digital waveform where information is encoded by its frequency. This type of conversion is highly applicable at every technology node and the time encoded output is considerably more robust than the voltage output of conventional amplifiers when considering supply noise and the process, voltage and temperature (PVT) variations. The time-domain concept has seen extensive use in recent publications because the voltage to frequency conversion provides high gain and exceptional dynamic range [^5][^4][^3] that can also accommodate conventional chopper techniques [^6][^7].
The conversion from analogue to frequency is not the only means by which analogue circuits can encode signals in the time-domain. It is well known that both synchronous [^8] and asynchronous [^9] oversampling modulators will generate a pulse-width-modulated (PWM) output bitstream. However these realisations conventionally do not perform integration in the time-domain and instead use charge pumps that suffer from typical drawbacks in advanced CMOS technologies such as gain degradation and limited voltage swing [^10]. In contrast the modulating characteristic of oscillators can negate component mismatch in any proceeding digital-to-analogue conversion since the digital output inherently provides data-weighted averaging [^5].
{{< figure src="/images/jssc2018/obi.svg" title="Figure 1: The proposed Analogue-to-Time Converter (ATC) that provides closed loop conversion of an analogue input voltage into an asynchronous multi-bit digital data stream." width="500" >}}
In order to retain high performance and minimise the requirement of ideal analogue components, time-based systems should be designed in a fashion where only small error signals are processed in the analogue domain with constrained linearity. Signals with large dynamics should be time-encoded and manipulated with robust digital logic. The proposed ATC realisation that follows this concept is shown in Fig. 1. This topology presents an asynchronous delta-sigma modulator (ADSM) that accumulates a phase difference between two oscillators to realise time-based integration and utilises capacitive feedback to linearise the conversion.
Here the sensor's voltage fluctuations on V<sub>IN<sub> modulate the pulse width of the PWM signal generated by the phase detector by combining multiple phases from each stage in the oscillator. In this fashion the output bit-stream D<sub>OUT<sub> can in effect resolve finer quantisation levels. In contrast to prior oscillator-based systems that are clocked, the asynchronous operation proposed here enables high-speed signal processing with oscillator-based filters [^11] or a continuous-time digital core [^12]. Both avoid the need for a high speed clock when processing a large number of recording channels and can therefore enable substantial power saving.
This work is a first step towards realising a sensor system that fundamentally only processes using time-encoded signals and can potentially operate using a supply voltage of only several hundred millivolts since the circuit can accurately convert millivolt level signals without prior analogue signal amplification [^14][^13]. This is because oscillator based integrators can operate with a voltage headroom close to transistor threshold voltage without diminishing loop gain or dynamic range. This advantage is not diminished by practical issues and large common-mode interference or electrode offset can be rejected because the sensor input is capacitively coupled to the main feedback loop. There are a number of established techniques such as using a DC servo loop or performing ripple rejection that prevent these issues from degrading circuit performance [^15]. This means that the voltage appearing at V<sub>X<sub> well controlled through feedback and that the amplifier can maximise power-efficiency-factor (PEF) [^16] without requiring additional voltage overhead to accommodate voltage fluctuation at its input.
This paper presents the implementation and modelling aspects of the oscillator based ATC using the following organisation: Section 3 details the instrumentation topology and Section 4 describes the corresponding transistor level implementation, Section 9 discusses the impact of technology and mismatch parameters of this circuit, Section 12 presents the measured results of a fabricated prototype, and Section 13 concludes this work.
# 3 Concept and ATC Architecture
This section introduces the operating principle and circuit dynamics of the proposed instrumentation system that is used to sense intra-cortical neural activity using a conventional electrode instrumentation setup. Such a scenario would record activity in-vivo or ex-vivo from the 1 Hz to 10 kHz frequency band where the signals are no larger than a few millivolts in amplitude[^17]. The circuit sensitivity must match the noise characteristics of the electrode or biological tissue and target a noise floor of around 50 nV/\rtxt{Hz}[^18]. These sensitivity conditions require the circuit dissipate several microamps and easily leads to a circuit bandwidth much larger than 10 kHz. For this reason this ATC will provide gain for a bandwidth exceeding 10 kHz since it is more resource effective to rely on proceeding processing stages to perform filtering when necessary.
{{< figure src="/images/jssc2018/obi_sys.svg" width="500" >}}
{{< figure src="/images/jssc2018/obi_blk.svg" title="Figure 2: Detailed system topology in a) and equivalent analytical model in b) of the proposed chopper stabilised ATC." width="500" >}}
A block diagram of the proposed architecture is detailed in Fig. 2a. For clarity, this shows the single ended equivalent of the fully differential circuit that was implemented. The difference in potential between two electrode inputs V<sub>R<sub> & V<sub>IN<sub> is chopped at the chopper frequency f<sub>chp<sub> to generate a up-modulated voltage waveform that couples the input onto V<sub>X<sub> through C<sub>I<sub>. The essential mechanism here is that signals appearing on V<sub>X<sub> induce a current that feeds into two oscillators with different polarities after being demodulated. This current forces the oscillators accumulate a relative phase difference because the phase is dependent on the integral of injected current [^19]. This phase difference is then evaluated for each oscillator tap using XOR logic to yield multiple time-encoded PWM signals that can also be chopped using digital logic. The resulting digital signal is capacitively coupled onto V<sub>X<sub> in parallel to close the loop. This is the main signal amplifying path that realises a first-order asynchronous ΔΣ modulator and this sense using N phase detectors in parallel represents asynchronous quantization of the phase difference with a resolution of log<sub>2<sub>(1+N) bits. Using this interpretation we can construct the corresponding analytical model that is shown in Fig. 2b and will assist in deducing the design's parameter dependencies.
$$ H(s) = \frac{ 1 }{ s / k_1 + N f } \approx \frac{1}{s\cdot \frac{N C_{gate} V_{RG}}{Gm}+\frac{C_F}{C_I}\frac{C_U}{C_U+\:\:\text{\makebox[-3pt][l]{\\(\nearrow\\)}}C_G/N}} $$
$$ f = {\frac{C_F}{C_{I}+C_{F}}} \cdot \frac{N C_{U}}{C_{F}+N C_{U}+ \text{\makebox[-3pt][l]{\\(\nearrow\\)}}C_{G}} $$
First the expression in Eq. 1 can be derived to characterise the signal amplifying loop. The feedback factor \\(f\\) evaluated in Eq. 2 corresponds to the capacitive coupling of a particular PWM phase Q on to V<sub>X<sub> with respect to the capacitors C<sub>I<sub>, C<sub>F<sub>, C<sub>G<sub>, C<sub>U<sub>. In this case C<sub>G<sub> can be digitally tuned to provide varying gain settings (41-53 dB). The oscillator's integration factor k<sub>1<sub> is derived by evaluating the impulse sensitivity function (ISF). The ISF captures how the oscillator phase is affected as a function of charge being injected into the virtual supply of the oscillator V<sub>R<sub> [^19]. Following the derivation for Eq. 2 in [^11] this factor can be assumed constant and is simply dependent on the transconductance Gm, loading capacitance of each delay stage C<sub>gate<sub>, and the voltage across the oscillator V<sub>RG<sub> such that k<sub>1<sub>=Gm/(N C<sub>gate<sub> V<sub>RG<sub>).
The second control loop is used to reject near-DC aggressors that will appear at the input of the main transconductor. Chopping will prevent the input-referred noise profile from being corrupted by flicker noise but in turn several large tones will appear at harmonics of f<sub>chp<sub> because off-set is being up-modulated. Moreover because this structure is not providing narrowband amplification the feedback must actively suppress these tones to avoid the output from being saturated and distorted. These components are integrated with a gain of approximately A<sub>ripple<sub>=k<sub>1<sub>/f<sub>chp<sub> which induces a 90\\(^\circ\\) phase shift. The phase-shift can be corrected for by using the chopper clock that is delayed by 1/4<sup>th<sup> of the period when demodulating Q to recover the off-set. The flicker rejection further depends on the transfer function F(s) which represents how the recovered signal is smoothed and fed back onto V<sub>X<sub>. Using a charge pump in addition to the pseudo-resistor R<sub>P<sub> will yield an expression for F(s) according to Eq. 3 where C<sub>L<sub> and I\tss{Δ} represent the main integration capacitor and charge pump bias current respectively. This is also shown in Fig. 2.
$$ F(s) = \frac{N I_{\Delta}}{s (C_{L} C_{I} R_{P} s + C_{L} + C_{I})} $$
Combining F(s) and A<sub>ripple<sub> will then predict how the noise aggressors at V<sub>x<sub> are removed. The frequency dependent response in Fig. 3 evaluates this control mechanism at different points in the loop using the following implemented circuit parameters: N=5, f<sub>chp<sub>=75 kHz, C<sub>I<sub>=288 fF, C<sub>G<sub>=69 fF, C<sub>F<sub>=C<sub>U<sub>=14 fF, R<sub>P<sub>=100 MΩ, C<sub>L<sub>=1.6 pF, I\tss{Δ}=5 nA. This shows the influence of noise at the input (e²<sub>flk<sub>) with respect to the ripple at the ATC output and the fluctuations on V<sub>X<sub> as a function of frequency. First notice the increased chopper frequency enables this circuit to increase its bandwidth and reject more of the low-frequency band including common-mode signals that asymmetrically couple onto V<sub>X<sub>. In addition the second order low-pass characteristic provides increased rejection of the chopper and oscillator tones such that the two control loops operate in isolation. A known drawback of increasing f<sub>chp<sub> is the reduction in input impedance but as shown in Sec. 10 this reduction can be mitigated with technology scaling and using a smaller value for C<sub>I<sub>.
{{< figure src="/images/jssc2018/noise_tf.svg" title="Figure 3: The closed loop response of the flicker rejection loop due to input-referred noise e²<sub>flk<sub> evaluated with respect to the ripple magnitude seen at Q (solid), the feedback seen at V<sub>X<sub> (dotted), and the open loop response F(s)\\(\cdot\\)A<sub>ripple<sub> (dashed)." width="500" >}}
Given these dynamics there is still important distinction to be made with regards to the rate of information seen at the output and the 3 dB bandwidth for signal amplification that in this case is the product of \\(f\\) k<sub>1<sub>\\(\approx\\)250 kHz. The digital output will encode an effective number of bits (ENOB) that relates to the ATC's precision (i.e. SNDR) and presents pulse width information of every cycle that in this case is oversampled by N parallel phases. However for one phase the entropy rate can be estimated in terms of f<sub>osc<sub> (SNDR-1.76)/6.02. This highlights an important motivation for time-domain processing since this information rate may easily be 10\\(\times\\) larger than a clocked digital bit-stream that maximally yields 1 bit per clock cycle. Optimistically this implies that time-domain techniques achieve a proportional boost in power efficiency since the digital power dissipation is a function of f<sub>osc<sub> even though a higher rate of information is being processed. For the latter to hold we must require the analogue and oscillator sub-blocks to operate with negligible power budget.
# 4 Circuit Implementation
{{< figure src="/images/jssc2018/obi_sch.svg" title="Figure 4: The transistor level implementation of the ATC circuit in Fig. 2a. Here the complementary structure in a) represents the main transconductor; b) represents the pseudo-differential oscillator where each delay cell is shown in c); The flicker rejection stage is shown in d) where only the grey section is replicated for each phase. Note that all devices have their body connected to the corresponding supplies with the exception of M\tss{5-8} which have the body connected to the drain of M<sub>9<sub>. Furthermore M\tss{13-16} and M\tss{21-22} their body connected to V<sub>R<sub> and either terminal of C<sub>L<sub> respectively." width="500" >}}
The transistor schematic for the proposed ATC is presented in Fig. 4 and the sizing of each device is listed in Table 1. This circuit can be segmented into four parts corresponding to the transconductor, oscillator, delay stage, and flicker rejection circuit. Each sub-block, including the capacitor array, will be described below. This configuration uses two bias voltages V<sub>BN<sub> & V<sub>BP<sub> to source the annotated drain currents. Both of these voltages are derived on-chip using a simple current mirror structure and a 1 μ A off-chip reference. Furthermore an external reference voltage V<sub>C<sub> is used to control the common mode voltage of V<sub>R<sub> that is placed at V<sub>DD<sub>/2. Note that the 65 nm technology used here provides transistors that can be configured with 150 mV (lvt), 250 mV (vt), and 350 mV (hvt) threshold voltages (V<sub>TH<sub>). The lvt option is used exclusively to reduce the supply voltage to 0.5 V with the exception of M\tss{23-24} which use a 250 mV threshold.
Table 1: Device Sizing in micrometers with the labels from Fig. 4
| Device | Size (W/L) | Device | Size (W/L) |
|----|----|----|----|
| M<sub>0<sub> | 26/5 | M\tss{15-16} | 0.2/2.5 |
| M\tss{1-2} | 16/0.25 | M\tss{17-18} | 2/5 |
| M\tss{3-4} | 2/1 | M\tss{19-20} | 10/0.2 |
| M\tss{5-6} | 4/0.5 | M\tss{21-22} | 1.6/0.4 |
| M\tss{7-8} | 0.8/1.4 | M\tss{23-24} | 0.96/4 |
| M<sub>9<sub> | 32/0.1 | Logic | 0.3/0.1 |
| M<sub>10<sub> | 6/5 | Switch<sub>CHP<sub> | 1/0.1 (P<sub>type<sub>) |
| M\tss{11-12} | 1.5/2.4 | Switch<sub>X<sub> | 1/0.2 (N<sub>type<sub>) |
| M\tss{13-14} | 2.3/2.5 | C<sub>L<sub> | 21/21 |
## 5 Low-Noise Transconductor
The complementary style transconductor (Fig. 4a) is adopted from [^20] to exploit two aspects of oscillator based integration. The first is that the operating conditions and transistor characteristics do not influence the loop gain of the time-based integrator but rather effect the noise characteristics which are already improved due to current recycling. Secondly the voltage fluctuation across V<sub>X<sub> & V<sub>S<sub> is negligible particularly if all transistors in the Gm cell and oscillator are in sub-threshold operation. This implies that the circuit can operate reliably with a narrow V<sub>DS<sub> margin for each transistor since the gate voltage V<sub>X<sub> is carefully controlled in closed loop and there is little concern for instability. The self-biasing cascodes M<sub>3,6<sub> biases each input pair with a V<sub>DS<sub> that is highly correlated with the threshold voltage and provides abundant dummy devices to improve matching. The cascodes also reduce the parasitic gate capacitance of the transconductor by reducing the Miller effect that may otherwise lead to increased noise.
Achieving good noise performance for this configuration relies on minimising the drain current noise from each transistor in the oscillator when referred to the input[^7]. As the ratio I<sub>M10<sub>/I<sub>M0<sub> is reduced the NEF of this circuit will asymptotically decrease to the optimal value for this topology (i.e. η\rtxt{2})[^21]. On the other hand I<sub>M10<sub> controls the oscillation frequency which must be sufficiently large such that the oscillator harmonics lie out of band similar to the chopper harmonics.
The lack of filtering requirements allows the asynchronous implementation to chose a large f<sub>osc<sub> by reducing C<sub>gate<sub> such that any intermodulation products with f<sub>chp<sub> do not fall in-band [^22] and the circuit size is minimised. When using this configuration as a clocked ΔΣ modulator[^23] this freedom is lost because k<sub>1<sub> must be directly related to the oversampling ratio. If the system can afford a fast oversampling clock f<sub>osc<sub> can still be large but it would be more effective to chose f<sub>osc<sub> close to the Nyquist frequency such that the harmonics of f<sub>osc<sub> can be removed reliably during decimation as they have already be shaped by the loop-filter. This circuit also constrains the minimum value for N due to the limited linearity of the transconductor for a given input range. This is because the ratio 2V<sub>DD<sub> \\(f\\)/(N+1) determines the maximum peak-to-peak amplitude of the error signal seen at V<sub>X<sub>. Fortunately for high-gain applications \\(f\\) is small resulting in sub-millivolt signal at V<sub>X<sub> and therefore high linearity can be achieved while using just a few phases in parallel.
## 6 Pseudo-Differential Oscillator
The main feature of the oscillators (Fig. 4b) used by this ATC is that it uses differential logic and the delay stage (Fig. 4c) is biased around the middle of the supply making the digital buffers for phase detection more power efficient. The corresponding advantages are best contrasted with a simple inverter delay cell that uses a capacitive load to ground. First the inverter based implementation would experience voltage spikes on V<sub>R<sub> due to discontinuous conduction of current but would also contaminate the ground with the AC current pulses. The configuration adopted from [^24] exhibits continuous charging & discharging currents that can be confined within the virtual supply nodes V<sub>G<sub>/V<sub>R<sub>. Moreover using switching transistors that are several μ m² in size to load for the preceding gate reduces the sensitivity to process variation with smaller area requirements since the transistor gate capacitance achieves a higher density than poly-poly or metal-oxide-metal (MOM) capacitors.
## 7 Flicker Rejection Stage
The flicker removal circuit (Fig. 4d) biases the input of the transconductor by feeding back common mode and differential mode signals using a cross coupled load to enable low voltage operation without an additional common-mode-feedback circuit[^20]. The differential feedback provides flicker cancellation by demodulating the digital output using a switched current DAC that integrates on C<sub>L<sub> which is a large vertical metal-insulator-metal (MIM) capacitor placed over the analogue circuitry. The diode connected devices M\tss{21-22} represent pseudo-resistors of 100 MΩ that provide a resistive path to V<sub>X<sub> and further smooths high frequency tones from f<sub>chp<sub> and f<sub>osc<sub>. A significant variation in resistive value is inherently expected but it is important to note that it does not influence the signal amplifying path and the non-dominant poles are far away from the 8 kHz bandwidth of F(s) in Eq. 3 by virtue of not using a second analogue integrator that may compromise stability. The common mode feedback regulates V<sub>R<sub> with respect to V<sub>C<sub> by biasing the common mode of V<sub>X<sub>. For this loop the gain arises from transconductance ratio gm\tss{M19-M20}/gm\tss{M23-M24} together with the drain resistance ratio rds<sub>M10<sub>/(rds<sub>M0<sub>+rds<sub>M9<sub>). This readily provides over 30 dB of gain with the dominant pole provided by the pseudo-resistors that will also attenuate the input common mode signals.
## 8 Capacitive Feedback Network
Both electrode inputs feed into separate capacitor arrays that off-set the scaled PWM signal generated at the output to calculate the differential error signal on V<sub>X<sub>. Each array is 20\\(\times\\)23 μ m² in size and uses 28 elements in a 4 by 7 configuration with 2.7\\(\times\\)2.7 μ m² horizontal MOM capacitors with 6 fingers on metal layers 2-7. The following allocation is used: C<sub>I<sub>=17\\(\times\\), C<sub>F<sub>=1\\(\times\\), C<sub>U<sub>=5\\(\times\\), C<sub>G<sub>=[0-5]\\(\times\\). The particular configuration in Fig. 2 can readily accommodate changes in dynamic range or adjustments in N. This is because \\(f\\) is dominated by the ratio C<sub>F<sub>/C<sub>I<sub> such that the design can freely change the number of phases being fed back without significantly changing the amplification dynamics. Additionally increasing C<sub>F<sub> will extend the dynamic range of the circuit since the noise floor will remain unchanged while providing less signal gain and having excessive circuit bandwidth.
# 9 The Impact of Technology Parameters
This section further highlights two features of the proposed topology that can be taken advantage of in advanced CMOS technologies where mismatch and process variation are the leading concern for designers. First we will summarise the scaling properties that arise when chopping in the input signal and secondly we will show that also for the asynchronous case the time-domain integration fundamentally helps with mitigating mismatch in digital to analogue conversion using a behavioural model as example.
## 10 CMOS Scaling of Chopper Impedance
First consider the input impedance R<sub>IN<sub> of the simple chopper structure used here[^25]. For sensor applications it is essential to maintain a large input impedance that avoids signal attenuation because many integrated sensors exhibit a source resistance of several M\\(\Omega\\).
$$ C_{I} = 10 C_{GM} = \frac{20}{3} W L C_{ox} $$
$$ f_{chp} = 2 f_{cor} = \frac{2 K_F}{W L C^2_{ox} e^2_{gd}} $$
The expression in Eq. 4 is first used select C<sub>I<sub> as 10\\(\times\\) the parasitic capacitance C<sub>GM<sub> seen on V<sub>X<sub> due the transconductor. This configuration avoids degrading the noise performance during amplification[^17]. C<sub>I<sub> is further equated in terms of the width W and length L of the input transistors. The chopper frequency is placed at exactly twice the corner frequency f<sub>cor<sub> which is the frequency at which the flicker noise is equal to the thermal noise floor e²<sub>gd<sub> of the target input-referred noise profile. Rearrangement of the terms will yield Eq. 5 which uses the trap density K<sub>F<sub> to estimate for flicker noise for a specific fabrication process[^26].
$$ R_{IN} = \frac{1}{2 C_{I} f_{chp} } = \frac{ 3 C_{ox} e^2_{gd} }{80 K_F } $$
{{< figure src="/images/jssc2018/sizing.svg" title="Figure 5: Chopper based input impedance as a function of CMOS technology using typical process parameters K<sub>F<sub>=3.2e-38 and C<sub>ox<sub>=1.6e-12 [F/μ m²]/L where L is the technology feature size in nanometre with the oxide thickness being estimated as 1/50 times the feature size." width="500" >}}
Eq. 6 calculates the expected input resistance and provides a first order estimation of amplifier impedance with respect to process parameters. The fact that R<sub>IN<sub> depends linearly on C<sub>ox<sub> implies that input resistance can be improved by using more advanced technologies. The expected values for R<sub>IN<sub> are plotted in Fig. 5 as a function of CMOS technology with varying noise requirements. Eventually the gate leakage will inhibit this trend as the associated shot-noise limits the sensitivity for technologies beyond 65 nm. This result primarily constrains the selection of transistor size[^25] that in turn determines f<sub>chp<sub> and f<sub>osc<sub>.
## 11 Modulated Mismatch in Oscillators
Mismatch due to process variation is the primary cause of distortion during multi-bit signal conversion. Minimising this source of nonlinearity is essential for both synchronous and asynchronous ΔΣ modulators because mismatch in the feedback DAC is not shaped by the loop filter [^27]. Fortunately the modulating property of the oscillator can remove this distortion if the phase readout is performed in a parallel fashion [^5]. Here we will concisely demonstrate that property arises because the mismatch induced components are simply being averaged and induce a DC-offset together with tones at the harmonic components of f<sub>osc<sub>. This uses a mapping that relates the phase difference \\(x\\) to the generated PWM waveform as a function of time \\(\tau\\) defined in Eq. 7. The following expression in Eq. 8 then evaluates the analogue feedback voltage that appears on V<sub>X<sub> in the ideal case for a given a phase difference of Δφ between the two oscillators.
$$ A(\tau,x) \triangleq\begin{cases} 1 & \tau (mod\: 1) \: < \:x 0 & \text{otherwise} \end{cases} $$
$$ V_{X}(t) = f \cdot \sum_{k=0}^{N-1} \underbrace{A( t \cdot f_{osc}+\frac{k}{N}\:,\: \Delta \phi )}_{Q_{k}(t)} $$
$$ Q_{k}(t) = (1+\frac{\sigma_{C,k}}{C_U}) A( t \cdot f_{osc} + \frac{k}{N} \: , \: \sigma_{\tau-\mu,k} + \Delta \phi) $$
There are two independent sources of mismatch for each phase: the deviation in capacitor weights of C<sub>U<sub> σ<sub>C,k<sub> and the differential delay variation in oscillator stages as a fraction of the oscillation period σ\tss{τ,k} that includes the digital gates generating Q (i.e. inverters and XOR-gate). These are used to formulate Eq. 9 which considers a particular phase of Q(t) and the random mismatch variables that have process dependent normal distributions. The variation in delay will locally increase/decrease the pulse-width of Q for a specific phase \\(k\\). This is a time-invariant component of the gate delay while Δφ and T<sub>osc<sub> are signal dependent. Precisely formulating the cumulative variation of σ\tss{τ} will relate the transistor sizing, gate capacitance, and threshold voltage of each delay during operation.
Notice that A is a linear function of Δφ with a gain of 1 for the DC component of the PWM output which can be further expanded to extract the high frequency behaviour. However by design these components are intentionally avoided which should reveal that that the capacitor weights are always uniformly averaged irrespective Δφ. Closed-loop operation feeds back each σ\tss{τ,k} such that the sum all components has zero mean, that is σ\tss{τ-μ,k}\ = σ\tss{τ,k}-(\\(\sum_{k=0}^{N-1}\\) σ\tss{τ,k}/N). The residual variation in delay for each phase inevitably induces spurs at at harmonics of f<sub>osc<sub>.
{{< figure src="/images/jssc2018/vco_model.svg" title="Figure 6: A continuous-time multi-phase VCO model for evaluating parameter sensitivity with transient simulations using the logical operator **B** in Eq. 10." width="500" >}}
Verifying this behaviour is best done by modifying the behavioural model commonly used for oscillators[^28] to accommodate multi-phase readout using the above expressions. Such a model is shown in Fig. 6. This configuration uses an internal time variable at V<sub>T<sub> that accumulates according to f<sub>osc<sub>. Given a set of quantisation levels L<sub>k<sub> or equivalently the number of phases, a logical function **B** will compute the corresponding PWM waveform of Q which are weighted by the associated capacitor C<sub>k<sub>. In this case the digital gate delay arising from computing the phase difference and applying feedback to the capacitive DAC can also be modelled by adjusting τ<sub>dly<sub>.
$$ \begin{split}\mathbf{B}(\phi_{S},\phi_{R},L) \triangleq & \left(\phi_{S} > L > \phi_{R} \right) \lor \left(\phi_{S} < \phi_{R} < L \right) & \lor \left( L < \phi_{S} < \phi_{R} \right)\end{split} $$
The logical expression in Eq. 10 simply compares the two phases with respect to L and evaluates the digital condition for which the output should be high. This representation implies that the delays correspond to the interval between each level which can be distributed uniformly as L<sub>k<sub>=(0.5+k)/L for integers k from 0 to N-1. By distributing the quantisation levels from 0 to 1 the corresponding delays are inherently normalised to the periodicity of φ\tss{S/R} without explicitly having to compute values with respect to f<sub>osc<sub> even when it is dynamically changing. In addition a difference in oscillator frequency between X\tss{1-2} can also be accommodated by adding a second integrated frequency component to the summation node.
{{< figure src="/images/jssc2018/dac_mm.svg" title="Figure 7: Simulated output spectrum with a 2.5 kHz input at -6 dB of the full input-range for a equivalent asynchronous flash quantiser with 2.6 bits of resolution and 5 % mismatch in σ\tss{τ,k} and σ<sub>C,k<sub>." width="500" >}}
{{< figure src="/images/jssc2018/dac_mm2.svg" title="Figure 8: Simulated output spectrum with a 2.5 kHz input at -6 dB of the full input-range for a asynchronous VCO quantiser with 2.6 bits of resolution, 300 kHz f<sub>osc<sub> and 5 % mismatch in σ\tss{τ,k} and σ<sub>C,k<sub>." width="500" >}}
Now the impact of mismatch can be simulated by adding parameter variation in the quantiser levels and the feedback weights (f). The analogous case where the mismatch is not modulated (i.e. f<sub>osc<sub> is 0) loosely corresponds to a flash-based ADC since the phase is simply being compared with N thresholds. The corresponding spectra of the flash quantiser is shown in Fig. 7 and oscillating quantiser is shown in Fig. 8 where we observe the distortion components in different bands of the spectrum.
# 12 Measured Results
{{< figure src="/images/jssc2018/micrograph.svg" title="Figure 9: Micro-photograph of the fabricated prototype showing an annotated floor plan in (a) and the poly layer together with the first three metal layers of the circuit layout in (b)." width="500" >}}
{{< figure src="/images/jssc2018/setup.svg" title="Figure 10: Experimental setup used for characterising the ATC for low-noise signal conversion showing the respective instruments that were used." width="500" >}}
The commercially available TSMC 65 nm CMOS LP MS RF technology (1P9M 6X1Z1U RDL) was used to prototype the proposed circuit and demonstrate measured noise and linearity characteristics. The chip micro-photograph of this prototype is shown in Fig. 9. The setup used to take these measurements is shown in Fig. 10 and uses a custom PCB to regulate V<sub>DD<sub> on-board with additional decoupling.
The external biasing allows this setup to first tune the circuit sensitivity by adjusting the 1 μ A reference current which scales all bias currents proportionally and then using V<sub>C<sub> the oscillation frequency can be fine tuned as V<sub>R<sub> is controlled which modulates I<sub>M10<sub>. The supply voltage can be tuned but reducing the supply below 0.5 V limits the biasing current and reduces the circuit sensitivity. Similarly increasing the supply is mainly constrained by the buffers that digitise the oscillator waveform and can induce a large leakage current beyond a voltage of 0.65 V.
The tone generated by the Agilent signal generator is attenuated resistively by a factor of 10 to achieve a low-noise differential test signal at the input of the instrumentation circuit. Two phases from the asynchronous output Q are captured at 500 MS/s using high-speed digital scope which can then be post-processed off-line to investigate the features of separate PWM signals during different operating conditions. Both the chopper tones and PWM carrier can be observed outside the signal bandwidth at harmonics of 78 kHz and 350 kHz respectively.
The characterisation procedure evaluates the signal to noise and distortion ratio (SNDR) for varying input amplitudes and frequencies. For a particular device, this characteristic is shown in Fig. 11. In extension, Fig. 12-13 show the distortion components as a function of amplitude along SA and the frequency along SF respectively. Fig. 14 shows what the input-referred power-spectral-density of Q looks like for a particular operating point at P. Here the lowest gain setting of 41 dB was used to demonstrate operation with maximum dynamic range. Although the circuit bandwidth theoretically exceeds the range of frequencies resolved here, the interfering tones seen in Fig. 14 prevent inaccurate measurements to confirm this result. Using a similar procedure the CMRR is characterised and shown in Fig. 15. Again, Fig. 17-16 show the distortion components due to a common mode input as a function of amplitude along SA and frequency along SF respectively. Due to the limited voltage overhead from the current sources in the transcondutor the high-frequency common-mode interference can result in degenerated operation as they are not attenuated by the pseudo-resistor. This mode of failure where the oscillators are saturated is out-lined by the dashed region.
Note that flicker noise from each oscillator is not removed by the chopper configuration in Fig. 4. However there is no apparent 1/f noise profile in the 10-100 Hz band even though the oscillators are small in size. This is because the rms-gate-voltage fluctuation due to flicker noise at each device is scaled by the open-loop gain of the ATC when referred to the input.
The maximum achieved THD was 60 dB for a 1 kHz sinusoidal input. The main source of performance degeneration in this circuit for larger input signals is due to the use of poorly regulated bias currents in the differential pair and relying on pseudo-differential phase read-out that allows some common-mode fluctuation at V<sub>S<sub> to couple to the output Q. Either introducing cascodes or using a folded cascode topology may improve linearity at the cost of increasing the required voltage headroom or reducing the noise efficiency. However the dynamic range exceeding 50 dB should be sufficient for the physiological range of amplitudes for neural activity given that there are no external aggressors present during recording. We can further confirm the effectiveness of the mismatch rejection technique as the Monte Carlo simulation results indicate that each phase should exhibit 1.1 % standard deviation in coupling factor for a 3-σ\: confidence interval. This should lead to a similar distortion characteristic shown in Fig. 7 with a large number of dominant harmonics being generated due to mismatch errors. Instead distortion is dominated by the second and third harmonic typical of more conventional analogue nonlinearity.
{{< figure src="/images/jssc2018/sndr_dm_sweep.svg" title="Figure 11: Characterisation sweep evaluating the SNDR performance using differential sinusoid at the input with varying amplitudes and frequencies. " width="500" >}}
{{< figure src="/images/jssc2018/thd_dm_vid.svg" title="Figure 12: Measured output harmonics due to a differential-mode 1 kHz input signal at different amplitudes corresponding to the SNDR measurement along SA in Fig. 11." width="500" >}}
{{< figure src="/images/jssc2018/thd_dm_frq.svg" title="Figure 13: Measured output harmonics due to a differential-mode 1.5 mVpp input signal at different frequencies corresponding to the SNDR measurement along SF in Fig. 11." width="500" >}}
{{< figure src="/images/jssc2018/spec_1k.svg" title="Figure 14: Measured output spectrum due to a differential 2 mVpp input signal at 1 kHz corresponding to the SNDR measurement at point P in Fig. 11." width="500" >}}
{{< figure src="/images/jssc2018/cmrr_cm_sweep.svg" title="Figure 15: Characterisation sweep evaluating the CMRR performance using large common-mode sinusoid at the input with varying amplitudes and frequencies." width="500" >}}
{{< figure src="/images/jssc2018/thd_cm_frq.svg" title="Figure 16: Measured output harmonics due to a common-mode 10 mVpp input signal at different frequencies corresponding to the CMRR measurement along SF in Fig. 15." width="500" >}}
{{< figure src="/images/jssc2018/thd_cm_vid.svg" title="Figure 17: Measured output harmonics due to a common-mode 1 kHz input signal at different amplitudes corresponding to the CMRR measurement along SA in Fig. 15." width="500" >}}
{{< figure src="/images/jssc2018/ccouple.svg" title="Figure 18: Measured frequency response due to differential 2 mVpp input signal that is capacitively coupled to the ATC input using 0.47 nF capacitors." width="500" >}}
The input impedance of this circuit was estimated by removing the resistive attenuation network and instead capacitively coupling the signal generator to the input. This assumes that the input will exhibit a RC time constant that is dominated by the coupling capacitor and the resistive/leakage component from the chopper in combination with the ESD protection that can be measured directly. The frequency dependent response is shown in Fig. 18. The 3dB cut-off frequency was estimated at 21.8 Hz. In this case two 0.47 nF capacitors were used to couple both inputs which implies the input resistance is around 31 MΩ. Parasitics at the input or capacitor variation can inflate this value and it is likely the impedance is closer to the analytical estimate of 22 MΩ \:according to Eq.6.
Table 2: System Characteristics and Comparison with State-of-the-Art
| Parameter [unit] | This Work | [^8] | [^29] | [^7] | [^6] | [^30] | [^31] | [^32] | [^33] | [^34] |
|----|----|----|----|----|----|----|----|----|----|----|
| Year | **2017** | 2017 | 2017 | 2017 | 2017 | 2016 | 2016 | 2015 | 2013 | 2012 |
| Application | **EAP** | ECG | LFP | - | LFP | ECG | EAP | EAP | EAP | EAP |
| Technology[nm] | **65** | 40 | 130 | 40 | 40 | 65 | 65 | 90 | 180 | 65|
| Modality | **Time** | Time | Volt. | Time | Volt. | Volt. | Volt. | Volt. | Volt. | Mix |
| Supply-V[V] | **0.5** | 0.6 | 1.2 | 1.2 | 1.2 | 0.6 | 1 | 1 | 0.45 | 0.5 |
| Supply-I[A] | \textbf{2.55 μ} | 5.5 μ | 5.3 μ | 14 μ | 2.5 μ | 3 n | 3.3 μ | 2.8 μ | 2.1 μ | 10 μ |
| Bandwidth[Hz] | **11 k** | 150 | 500 | 5 k | 200 | 370 | 8.2 k | 10.5 k | 10 k | 10 k |
| Input Range[mVpp] | **4** | 40 | - | 8 | 100 | 25 | 220 | 1 | 1 | 1 |
| CMRR[dB] | \textbf{(>)60(^\star)} | 60 | 90 | 97 | - | 60 | (>)80 | (>)45 | 73 | 75 |
| SFDR[dB] | **60** | 56 | 72 | 70 | 79 | 75 | (>)40 | (>)37 | (>)46 | (>)34 |
| Noise Floor[V/\rtxt{Hz}] | **36 n** | 0.6 μ | 46n | 32 n | - | 1.4 μ | 27.5n | 35n | 29n | 100n |
| RMS Noise[μ V<sub>rms<sub>] | **3.8** | 7.8 | 1.1 | 2.3 | 5.2 | 26 | 4.1 | 3.04 | 3.2 μ | 4.9 μ |
| Area[mm²] | **0.006** | 0.015 | 0.013 | 0.015 | 0.135 | 0.15 | 0.042 | 0.137 | 0.25 | 0.013 |
| NEF / PEF | \textbf{2.2 / 2.4} | 8.1 / 39| 2.9 / 10| 4.7 / 27| 22 / 581| 2.1 / 2.6| 3.2 / 10| 1.9 / 3.6 | 1.57 / 1.1 | 5.99 / 18 |
{{< figure src="/images/jssc2018/breakdown.svg" title="Figure 19: Power and area contributions from each sub-circuit." width="500" >}}
The detailed system characteristics are summarised in Table 2. The system power dissipation was specified at 1.3 μ W from these measurements. The relative power and area utilisation of each subcircuit is compared in Fig 19. As expected, a large fraction of both power and area is used by the main analogue circuits that consists of the low-noise transconductor and the flicker rejection stage. This distribution maximises the NEF and shows that the asynchronous digital logic can provide additional functionality without a significant resource overhead. In relation to the work in [^7], this ATC topology exhibits as significant reduction in power budget although input-referred noise figure is slightly increased. This improvement is not as pronounced in comparison with [^8] but instead the figure of merit is superior. Other works show that both time-based and voltage-based instrumentation can achieve near ideal noise efficiency but only select topologies enable more advanced CMOS process to yield a smaller silicon footprint. The pioneering work in [^34] already demonstrated that resource efficient signal acquisition is best realised by combing signal quantisation and amplification into a single loop. The main drawback was that this mixed signal topology was still relatively complex for hundreds of channels and linearising the feedback for closed loop quantisation came with a considerable reduction in noise efficiency. However the ΣΔ operation of the clocked VCO and the ΣΔ modulated DAC in the feedback enable a powerful technique that trades off excessive bandwidth for reduced circuit size or DAC complexity. The same technique is applied here to enable a compact multichannel configuration. Our future work will extend on the current prototype by additionally providing electrode off-set cancellation for \textit{in-vivo} experiments with multi-channel recording capabilities.
# 13 Conclusion
This work proposes a chopper-stabilised ATC to enable high-impedance electrode instrumentation for integrated sensing systems that require ultra low-voltage operation for power saving. The time-domain techniques enabled by this ATC topology alleviate the difficulty of performing precise instrumentation in advanced CMOS technologies while also providing improved power efficiency together with a substantial reduction in size. The presented configuration achieves a power budget of 1.2 μ W for a 36 nV/\rtxt{Hz} noise floor requirement and a compact silicon footprint of 0.006 mm². In extension to presenting the implementation details, this work also provides essential modelling and analytical tools for further optimisation. This will enable other mixed-signal systems that require high noise-efficiency, high-speed, or asynchronous signal conversion to effectively adopt time-based techniques and utilise the presented circuit implementation.
# 14 Acknowledgement
The authors would like to thank Dr. Pantelis Georgiou, and the Europractice Advanced Technology Stimulation programme for providing access to the TSMC 65 nm technology. The authors additionally thank Yan Liu and the anonymous reviewers for their valuable assistance with this manuscript.
# Refernces:
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[^2]: C.Huang and S.Chakrabartty, ''An asynchronous analog self-powered cmos sensor-data-logger with a 13.56 MHz RF programming interface,'' IEEE J. Solid-State Circuits, vol.47, no.2, pp. 476--489, Feb 2012.
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[^5]: K.Lee, Y.Yoon, and N.Sun, ''A scaling-friendly low-power small-area $\Delta \Sigma$ ADC with VCO-based integrator and intrinsic mismatch shaping capability,'' IEEE Trans. Emerg. Sel. Topics Circuits Syst., vol.5, no.4, pp. 561--573, Dec 2015.
[^8]: R.Mohan etal., ''A 0.6 V, 0.015-mm$^2$, time-based ECG readout for ambulatory applications in 40 nm CMOS,'' IEEE J. Solid-State Circuits, vol.52, no.1, pp. 298--308, Jan 2017.
[^6]: W.Jiang etal., ''A ±50 mV linear-input-range VCO-based neural-recording front-end with digital nonlinearity correction,'' IEEE J. Solid-State Circuits, vol.52, no.1, pp. 173--184, Jan 2017.
[^4]: P.Prabha etal., ''A highly digital VCO-based ADC architecture for current sensing applications,'' IEEE J. Solid-State Circuits, vol.50, no.8, pp. 1785--1795, Aug 2015.
[^3]: T.Anand, K.A.A. Makinwa, and P.K. Hanumolu, ''A VCO based highly digital temperature sensor with 0.034 $^\circ$C/mV supply sensitivity,'' IEEE J. Solid-State Circuits, vol.51, no.11, pp. 2651--2663, Nov 2016.
[^10]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-mode operational amplifiers and their application to continuous-time filters in nanoscale CMOS,'' IEEE J. Solid-State Circuits, vol.49, no.12, pp. 2758--2772, Dec 2014.
[^23]: L.B. Leene and T.G. Constandinou, ''A 0.5V time-domain instrumentation circuit with clocked and unclocked
Delta
Sigma operation,'' in 2017 IEEE International Symposium on Circuits and Systems (ISCAS), May 2017, pp. 1--4.
[^12]: Y.Chen etal., ''A continuous-time digital IIR filter with signal-derived timing and fully agile power consumption,'' IEEE J. Solid-State Circuits, vol.53, no.2, pp. 418--430, Feb 2018.
[^22]: S.Pavan, ''Analysis of chopped integrators, and its application to continuous-time delta-sigma modulator design,'' IEEE Trans. Circuits Syst. I, vol.64, no.8, pp. 1953--1965, Aug 2017.
[^24]: W.S.T. Yan and H.C. Luong, ''A 900-MHz cmos low-phase-noise voltage-controlled ring oscillator,'' IEEE Trans. Circuits Syst. II, vol.48, no.2, pp. 216--221, Feb 2001.
[^17]: R.R. Harrison and C.Charles, ''A low-power low-noise CMOS amplifier for neural recording applications,'' IEEE J. Solid-State Circuits, vol.38, no.6, pp. 958--965, June 2003.
[^19]: A.Hajimiri and T.H. Lee, ''A general theory of phase noise in electrical oscillators,'' IEEE J. Solid-State Circuits, vol.33, no.2, pp. 179--194, Feb 1998.
[^25]: T.Denison etal., ''A 2
muW 100 nV/rtHz chopper-stabilized instrumentation amplifier for chronic measurement of neural field potentials,'' IEEE J. Solid-State Circuits, vol.42, no.12, pp. 2934--2945, Dec 2007.
[^14]: Y.Li, D.Zhao, and W.A. Serdijn, ''A sub-microwatt asynchronous level-crossing ADC for biomedical applications,'' IEEE Trans. Biomed. Circuits Syst., vol.7, no.2, pp. 149--157, April 2013.
[^13]: W.Tang etal., ''Continuous time level crossing sampling ADC for bio-potential recording systems,'' IEEE Trans. Circuits Syst. I, vol.60, no.6, pp. 1407--1418, June 2013.
[^9]: G.D. Colletta etal., ''A 20 nW 0.25 V inverter-based asynchronous delta-sigma modulator in 130 nm digital CMOS process,'' IEEE Trans. VLSI Syst., vol.25, no.12, pp. 3455--3463, Dec 2017.
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[^29]: H.Kassiri etal., ''Rail-to-rail-input dual-radio 64-channel closed-loop neurostimulator,'' IEEE J. Solid-State Circuits, vol.52, no.11, pp. 2793--2810, Nov 2017.
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mu w/channel consumption in 0.18

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---
title: "Autonomous SoC for neural local field potential recording in mm-scale wireless implants"
date: 2018-07-23T15:26:46+01:00
draft: false
toc: true
type: posts
math: true
tags:
- publication
- CMOS
- wireless
- system-on-chip
- biomedical
---
Lieuwe B. Leene, Peilong Feng, Michal Maslik, Katarzyna M. Szostak, Federico Mazza, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
Next generation brain machine interfaces fundamentally need to improve the information transfer rate and chronic consistency. This needs them to be highly scalable but also to observe signals that are stable over time. Towards this aim, this paper presents a novel System-on-Chip (SoC) for a mm-scale wireless neural recording node that can be implanted in a distributed fashion. The proposed self-regulating architecture allows each implant to operate autonomously and adaptively load the electromagnetic field to extract a precise amount of power for full-system operation. This can allow for a large number of recording sites across multiple implants extending through cortical regions without increased control overhead in the external head-stage. By observing only local field potentials (LFPs), chronic stability is improved and good coverage is achieved whilst reducing the spatial density of recording sites. The system features a \\(\Delta\Sigma\\) based instrumentation circuit that digitises high fidelity signal features at the sensor interface thereby minimising analogue resource requirements while maintaining exceptional noise efficiency. This has been implemented in a 0.35 μ m CMOS technology allowing for wafer-scale post-processing for integration of electrodes, RF coil, electronics and packaging within a 3D structure. The presented configuration will record LFPs from 8 electrodes with a 825 Hz bandwidth and an input referred noise figure of 1.23μ V<sub>rms<sub>. The resulting electronics has a core area of 2.1 mm² and a power budget of 80 μW.
# 2 Introduction
There has been significant effort in developing integrated circuits for Brain Machine Interfaces (BMIs)[^1]. These systems enable a wide range of applications from recording neural signals for scientific study to treating neurological conditions. They integrate a multitude of functions for sensing, processing, telemetry and power management. There is a drive to develop wireless modules that are hermetically packaged for chronic implant applications[^2]. Moreover, any reduction in size can substantially improve device efficacy by reducing the impact on surrounding tissue. Any reduction in weight is also highly desirable for behaving animal studies. While a number of proposed systems have relied on PCB[^3] or flexible [^4] technologies that allow low cost, rapid development. This approach leads to substantially larger implants when compared to silicon-based integration[^1]. This is because the silicon substrate enables a large number of electrodes to be integrated directly onto the active die in the shape of an implantable shank[^5]. In contrast, making a large number of intra-device connections has a significant impact on device footprint as well as fabrication complexity with added bio-compatibility constraints [^6]. For this reason a number of groups are investigating millimetre-scale solutions for recording[^7] and stimulation[^8] with all aspects of the implant integrated within the silicon die or micro-machined package.
{{< figure src="Figures/ENGINI.pdf" title="Figure 1: The ENGINI concept showing: (a) multiple freely floating probes being wirelessly interrogated by a headstage unit; (b) schematic representation." width="500" >}}
The 'Empowering Next Generation Implantable Neural Interfaces' (ENGINI) project achieves its scalability by utilising multiple mm-scale probes that are each implanted and 'freely floating' in the cortex. These observe field potentials along the cortical column but also laterally through different probes. These are wirelessly coupled to an external headstage with trancutanious and transdural inductive links to deliver power and exchange data. This is illustrated in Fig. 1.
This particular system relies on the autonomous behaviour of each probe such that a downlink is not required and each probe simply backscatters recorded activity using load shift keying (LSK) modulated at different preconfigured frequencies derived from the carrier. This allows each probe to be uniquely identified without increased control overhead for larger ensembles of probes. The probe circuit additionally includes all front-end instrumentation. An aggressive strategy is thus needed to reduce system complexity to enable package miniaturisation. Such a system may therefore not be able to incorporate more advanced functionality found in the state-of-the-art[^9]. Instead the electronics will perform direct quantization of the 1-825 Hz local field potential (LFP) signal bandwidth that is transmitted directly without compression to allow long term recordings with sub-millimetre spacial resolution for chronic BMI applications. The rest of this paper is organised as follows: Section 3 details the overall system operation and high level implementation; Section 4 describes the circuit implementation; Section 8 presents simulation results and system characteristics; and Section 9 concludes this work with respect to the achieved performance.
# 3 System Architecture
The integrated system architecture is shown in Fig. 2. This shows a single recording unit which is inductively coupled to a primary coil L<sub>1<sub> that provides power using a 433 MHz carrier to leave sufficient bandwidth for frequency division multiplexing multiple recording units. In fact the receiving coil L<sub>2<sub> will be located on a passive undoped silicon interposer that is flip-chip bonded to the active instrumentation IC. The resonant tank L<sub>2<sub> C<sub>2<sub> receives the transmitted power and establishes a DC voltage on V<sub>DD<sub> once the rectifier down-converts the carrier. First a biasing circuit is powered that generates digital flags that indicate the supply voltage level. These flags assist the self-tuning control algorithm to adjust the loading capacitance C<sub>T<sub> to tune or detune the resonant tank L<sub>2<sub>C<sub>2<sub> and receive a specific amount of power to establish 1.5 V on the V<sub>DD<sub> supply. This feedback regulates the supply voltage in a course manner without needing active control from the primary side (external controller). This implies the analogue circuits need to accommodate for any fluctuations without diminishing sensor precision. The continuous-time fully-differential modulator topology will further prevent these supply noise aggressors from being aliased in-band during sampling. The system clock can be directly extracted from the resonant tank using adiabatic logic elements to implement a series of frequency dividers before passing the clock to the digital core[^10].
{{< figure src="Figures/SYS.pdf" title="Figure 2: ENGINI system architecture for recording LFP at high resolution. This tunes the receiving resonant tank L<sub>2<sub>C<sub>2<sub> to regulate V<sub>DD<sub>." width="500" >}}
# 4 Circuit Implementation
This ENGINI prototype has been developed for a 0.35 μ m CMOS technology such that assembly of the 3D probe can be performed in-house using low-cost micro-fabrication and micro-packaging techniques. The implementation of each subsystem will be detailed below.
## 5 Self-Regulated Power Harvesting
This provides a stable power supply for the electronics and back-scatters digitised recordings. The circuit architecture is shown in Fig. 3. This contains a binary weighted capacitor bank C<sub>T<sub>, a passive full wave rectifier, and a sensing circuit which are all digitally-controlled. The principle of operation can be described as follows. First, the cross-coupled rectifier converts the induced AC voltage to a DC power on V<sub>x<sub>. Then, the low voltage amplifier A<sub>2<sub> performs auto-zeroing by shorting C<sub>F<sub> and simultaneously sampling the rectified voltage onto C<sub>I<sub>. After sampling, the parallel binary-weighted capacitor bank C<sub>T<sub> is adjusted to tune or de-tune LC tank on the secondary side. There is therefore a voltage fluctuation at node V<sub>x<sub>. The change in V<sub>x<sub> is amplified 30\\(\times\\) by A<sub>2<sub> which corresponds to the ratio C<sub>I<sub>/C<sub>F<sub>. The polarity of the resulting change is digitised using the comparator, instructing the digital control to add or remove parallel capacitors in the next cycle of regulation. Two supply voltage level indicators from the biasing circuit further assist this feedback to increase or reduce the supply voltage and whether to perform LSK respectively. The resistor R<sub>z<sub> is added after the output of rectifier such that the speed at which V<sub>X<sub> can be controlled is not dependent on the load capacitance C<sub>L<sub> which may be quite large. This allows fast regulation with a clock speed of 846 kHz at the cost of some reduction in power efficiency due to the voltage drop from V<sub>X<sub> to V<sub>DD<sub>.
{{< figure src="Figures/REG.pdf" title="Figure 3: Adaptive power conversion and regulation circuit using full-wave rectifier, tunable LC tank, auto-zeroing amplifier and strong arm comparator" width="500" >}}
%
## 6 \\(\Delta\Sigma\\) Instrumentation Circuit
The instrumentation circuit used to acquire the electrode recordings is based on the time-domain \\(\Delta\Sigma\\) modulator in [^11]. This uses differential oscillators as the integration element with an asynchronous signal quantizer. However the implementation presented here introduces an additional Gm-C integrator and a feed-forward path to realise second-order noise shaping. This reduces the oversampling ratio (OSR) requirement and substantially increases the dynamic range of the system. A single-ended equivalent of the fully-differential structure used here is shown in Fig. 4.
{{< figure src="Figures/SDM.pdf" title="Figure 4: Simplified equivalent of the second-order \\(\Delta\Sigma\\) modulator using time-domain signal quantization exhibiting a bandpass response due to the switched current DAC which removes any electrode offset." width="500" >}}
%
Note that this is a DC-coupled configuration where the analogue node V<sub>O<sub> tracks the electrode potential. An electrode offset larger than \\(\pm\\)100 mV can be accommodated without saturating the modulator by adding the digitally switched and duty cycled current in the feedback path. The quantized signal Q is AC coupled onto V<sub>O<sub> with a relatively large attenuation factor due to capacitive division α=1/(C<sub>0<sub>/C<sub>C<sub>+1) which will allow the in-band signal gain. This can be confirmed using the small signal model for this circuit described in Eq. 1-4 where H(s) represents the second-order loop filter and C(s) the charge pump with capacitive feed-forward. The factor k1=OSR f<sub>smp<sub>/2 reflects the modulator bandwidth in terms of the target sampling frequency f<sub>smp<sub>. The factor k2=2\\(\pi\\) f<sub>hp<sub> represents the integration constant of the charge pump in terms of the high-pass cut-off frequency f<sub>hp<sub>. This approach is inspired by the first order modulator in [^12]. The implemented circuit uses an OSR of 64, a 1 Hz high-pass corner frequency, and third order CIC filter to decimate the output. This leads to the noise and signal transfer functions shown in Fig. 5.
$$ STF(s) = \frac{H}{1+\alpha C H} $$
$$ H(s) = \left( 2 + \frac{k1}{s} \right) \frac{k1}{\alpha s} $$
$$ NTF(s) = \frac{1}{1+\alpha C H} $$
$$ C(s) = 1 + \frac{k2}{s} $$
{{< figure src="Figures/BODE.pdf" title="Figure 5: Analytical quantisation noise and signal transfer functions of the proposed modulator configuration." width="500" >}}
## 7 Reference and Biasing Circuit
The reference circuit loosely based on [^13] is used to establish the required noise shaping and precision in the \\(\Delta\Sigma\\) modulators. This provides a stable bias current using the structure shown in Fig. 6. Its core entails a β-multiplier generating a reference current of 800 nA flowing through resistor R<sub>1<sub>. This is scaled and mirrored to generate 8 current sinks for the front-end. Generation of a nominal 1.2 V reference is achieved by passing the reference current through a diode-connected PNP BJT B<sub>1<sub> and multiplying the BE (base-emitter) voltage using amplifier A<sub>2<sub> with resistive feedback. As the output voltage V<sub>REF<sub> primarily depends on the BJT BE voltage and ratio of R<sub>2<sub> and R<sub>3<sub> it is possible to achieve a very accurate voltage output independent of process variation.
Since the circuit is going to be operated in a neural implant it is expected that its operating temperature is going to remain stable and it is therefore not necessary to optimise the circuit for temperature independence. The main design target therefore lies in maximisation of the achieved PSRR (Power Supply Ripple Rejection) and minimisation of power consumption. The PSRR of the β-multiplier is maximised by cascoding both PMOS and NMOS current mirrors (M<sub>1<sub>\&M<sub>2<sub>, M<sub>3<sub>\&M<sub>4<sub>) [^14]. The same is achieved for V<sub>REF<sub> by employing a regulated cascode for BJT current generation.
In addition, the reference circuit generates logic levels indicating that the supply voltage has reached \\(\approx\\) 1 V, 1.3 V and 1.5 V used by the control loop of the SoC. The first indicator (1 V) is designed using a current source inverter as described in [^15]. The remaining two indicators are derived from V<sub>REF<sub> to ensure good tolerance to process variations.
{{< figure src="Figures/refc.pdf" title="Figure 6: Schematic of the reference and biasing circuit (start-up circuit not shown)." width="500" >}}
# 8 Simulation Results
The circuit was designed and validated using PSP models from the commercially available AMS 0.35 μ m CMOS technology (C35B4C3 4M/2P/HR/5V).
Preliminary simulation results show the instrumentation achieves a thermal noise floor of 45 nV<sub>rms<sub>/\\(√{\text{Hz}}\\) and uses 2.25μ A of current from a 1.5 V supply including also the decimation filter. This indicates a 3.4 μ W power budget per recording channel. The decimated output is shown in Fig. 7, achieving a dynamic range larger than 80 dB since the maximum modulator input range is \\(\pm\\)6 mV excluding the \\(\pm\\)100 mV linear range of the charge pump feedback.
The designed reference circuit consumes a bias current of 5 μ A and generates an output nominal voltage V\tss{REF,μ}=1.208 V with a standard deviation of σ =10.87 mV as shown by post-layout Monte Carlo simulation of 500 runs. Similarly, the output bias current was found to be I\tss{REF,μ}=150.4 nA and σ <sub>IREF<sub>=15.6 nA. The mismatch between two different bias currents has a standard deviation of σ \tss{\\(\Delta\\)IREF}=5.35 nA. The PSRR of the reference voltage with respect to frequency can be seen in Fig. 8. This shows that the reference circuit features an almost flat frequency response and a PSRR higher than 70 dB at small and high frequencies.
The overall system specifications are summarised in Table 1. Comparing the ENGINI system with other SoCs for brain machine interfaces demonstrates an increase in dynamic range and reduction in core size for equivalent noise performance as a result of the proposed architecture. The active silicon CMOS is currently being fabricated and will be flip-chip bonded onto a silicon based carrier. The two dies are illustrated and annotated in Fig. 9. Both dies are 16 mm² in size however the interposer is passive and only needs to embed the seal, coil, and electrode interconnect metallisation. Preliminary characterisation has shown that the L<sub>2<sub> can have an inductance of 5 nH with a Q-factor \textgreater12.
{{< figure src="Figures/SPEC.pdf" title="Figure 7: Output spectrum of the \\(\Delta\Sigma\\) instrumentation circuit from transient simulation using a 10 mVpp sinusoidal input tone at 210 Hz." width="500" >}}
{{< figure src="Figures/PSRR.pdf" title="Figure 8: PSRR (Power Supply Ripple Rejection) at V<sub>REF<sub>. This shows a PSRR of μ =78.29 dB & σ =1.58 dB, μ =69.94 dB & σ =1.59 dB and μ =79.95 dB & σ =0.52 dB at DC, 64 kHz and 433 MHz respectively." width="500" >}}
Table 1: System Characteristics and Comparison with State-of-the-Art
| Parameter [unit] | This Work \\(\dagger\\) | [^1] | [^16] | [^3]|
|----|----|----|----|----|
| Year | **2017** | 2017 | 2015 | 2016 |
| Application | **LFP** | ECoG | ECoG | EAP |
| Tech.[nm] | **350** | 180 | 65 | 350 |
| Supply-V[V] | **1.5** | 0.8 | 0.5 | 1.8|
| Total-P[W] | \textbf{80 μ}(\star) | 0.1 m | 0.2 m | 51 m |
| Core-A[mm²] | **2.1** | 9 | 5.8 | 12.5 |
| \# Channels | **8** | 16 | 64 | 8|
| Bandwidth[Hz] | **825** | 1 k | 500 | 11 k|
| DR[dB] | **85** | 55 | 52 | 50 |
| IRN [μ V<sub>rms<sub>] | **1.3** | 1.5 | 1.3 | 2.9 |
\\(\dagger\\) Based on preliminary simulation results. \\(\star\\) Includes rectifier loss.
{{< figure src="Figures/D2D.pdf" title="Figure 9: Annotated design for each silicon die that will be flip-chip bonded together. This shows the bonding pads, inductive coil, seal ring, and core ENGINI system to scale." width="500" >}}
# 9 Conclusion
This work demonstrates a compact system on chip architecture for LFP based recording systems that aims to distribute several implantable probes into the cortical tissue in a scalable fashion by relying on autonomous sensor operation. Using the resonant tuning for supply regulation and \\(\Delta\Sigma\\) modulator instrumentation has lead to a significant reduction in system complexity typically seen in BMI SoCs. Moreover this configuration is able to operate at high efficiency without much constraint on technology requirements since the overall system power budget is estimated to be 80 μ W from preliminary simulation results. The approach to brain machine interfaces presented here will lead to safer and simpler systems while delivering high fidelity multi-electrode recordings which is essential for applications in a clinical environment.%
# 10 Acknowledgement
This work was supported by EPSRC grant EP/M020975/1.
# References:
[^9]: M.A.B. Altaf, C.Zhang, and J.Yoo, ''A 16-channel patient-specific seizure onset and termination detection SoC with impedance-adaptive transcranial electrical stimulator,'' IEEE J. Solid-State Circuits, vol.50, no.11, pp. 2728--2740, Nov 2015.
[^1]: S.Ha etal., ''Silicon-integrated high-density electrocortical interfaces,'' Proc. IEEE, vol. 105, no.1, pp. 11--33, Jan 2017.
[^16]: R.Muller etal., ''A minimally invasive 64-channel wireless $\mu$ECoG implant,'' IEEE J. Solid-State Circuits, vol.50, no.1, pp. 344--359, 2015.
[^8]: A.Khalifa, J.Zhang, M.Leistner, and R.Etienne-Cummings, ''A compact, low-power, fully analog implantable microstimulator,'' in IEEE Proc. ISCAS, May 2016, pp. 2435--2438.
[^7]: E.Moradi etal., ''Backscattering neural tags for wireless brain-machine interface systems,'' IEEE Trans. Antennas Propag., vol.63, no.2, pp. 719--726, Feb 2015.
[^6]: Y.K. Lo etal., ''A fully integrated wireless SoC for motor function recovery after spinal cord injury,'' IEEE Trans. Biomed. Circuits Syst., vol.11, no.3, pp. 497--509, June 2017.
[^11]: L.Leene, T.Constandinou etal., ''A 0.5 V time-domain instrumentation circuit with clocked and unclocked operation,'' in IEEE Proc. ISCAS, May 2017, pp. 2619--2622.
[^5]: C.M. Lopez etal., ''A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13$\mu$m SOI CMOS,'' IEEE Trans. Biomed. Circuits Syst., vol.11, no.3, pp. 510--522, June 2017.
[^4]: S.A. Mirbozorgi etal., ''A single-chip full-duplex high speed transceiver for multi-site stimulating and recording neural implants,'' IEEE Trans. Biomed. Circuits Syst., vol.10, no.3, pp. 643--653, June 2016.
[^12]: H.Kassiri etal., ''27.3 all-wireless 64-channel 0.013mm$^2$/ch closed-loop neurostimulator with rail-to-rail DC offset removal,'' in IEEE Proc. ISSCC, Feb 2017, pp. 452--453.
[^2]: D.A. Schwarz etal., ''Chronic, wireless recordings of large-scale brain activity in freely moving rhesus monkeys,'' Nature Methods, vol.11, pp. 670--676, April 2014.
[^15]: M.H. Cho etal., ''Development of undervoltage lockout (UVLO) circuit configurated schmitt trigger,'' in IEEE Proc. ISOCC, Nov 2015, pp. 59--60.
[^14]: G.Giustolisi and G.Palumbo, ''A detailed analysis of power-supply noise attenuation in bandgap voltage references,'' IEEE Trans. Circuits Syst. I, vol.50, no.2, pp. 185--197, Feb 2003.
[^13]: Y.Osaki, T.Hirose, N.Kuroki, and M.Numa, ''1.2-V supply, 100-nW, 1.09-V bandgap and 0.7-V supply, 52.5-nW, 0.55-V subbandgap reference circuits for nanowatt CMOS LSIs,'' IEEE J. Solid-State Circuits, vol.48, no.6, pp. 1530--1538, June 2013.
[^10]: S.Houri etal., ''Limits of CMOS technology and interest of NEMS relays for adiabatic logic applications,'' IEEE Trans. Circuits Syst. I, vol.62, no.6, pp. 1546--1554, June 2015.
[^3]: S.B. Lee etal., ''An inductively-powered wireless neural recording system with a charge sampling analog front-end,'' IEEE Sensors J., vol.16, no.2, pp. 475--484, Jan 2016.

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---
title: "Direct Digital Wavelet Synthesis for Embedded Biomedical Microsystems"
date: 2018-10-17T15:26:46+01:00
draft: false
toc: true
type: posts
math: true
tags:
- publication
- CMOS
- digital-logic
- signal-synthesis
- wavelets
---
Lieuwe B. Leene, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
This paper presents a compact direct digital wavelet synthesizer for extracting phase and amplitude data from cortical recordings using a feed-forward recurrent digital oscillator. These measurements are essential for accurately decoding local-field-potentials in selected frequency bands. Current systems extensively to rely large digital cores to efficiently perform Fourier or wavelet transforms which is not viable for many implants. The proposed system dynamically controls oscillation to generate frequency selective quadrature wavelets instead of using memory intensive sinusoid/cordic look-up-tables while retaining robust digital operation. A MachXO3LF Lattice FPGA is used to present the results for a 16 bit implementation. This configuration requires 401 registers combined with 283 logic elements and also accommodates real-time reconfigurability to allow ultra-low-power sensors to perform spectroscopy with high-fidelity.
# 2 Introduction
Spectrum analysis is an essential tool for many biomedical applications to provide electrode impedance characteristics[^2][^1] and assist in signal decomposition for brain machine interfaces (BMI)[^4][^3]. These techniques typically rely on generating a precise reference tone to characterise the spectral power distribution of a signal or analyse the frequency dependent response of a subsystem. However generating a sinusoid demands a significant mount of valuable hardware resources for both analogue[^5] and digital[^6] implementations and can inhibit an efficient solution. For this reason numerous techniques such as ΔΣ\:modulation[^7] and closed loop adaptive filtering[^8] have been proposed to reduce system integration costs and enhance the capability of biomedical sensing systems.
In line with these developments, this work proposes a hardware efficient direct digital wavelet synthesizer (DDWS) to extract both time and frequency information simultaneously. The DDWS extends on conventional direct digital frequency synthesis (DDFS) systems[^9] the same way the generalised s-transform[^10] extends on the Fourier transform by resolving the time-evolving frequency content of non-stationary signals. Current systems typically use the CT/DT wavelet-transform to extract this type of information because it is more hardware efficient than the windowed/short-time Fourier transform[^11]. However for applications like electrode-impedance spectroscopy and measuring phase synchrony in brain activity, wavelets cannot be used because the phase information is either not preserved or does not use a global reference leading to incomplete measurements. This presents an opportunity for mixed signal techniques to be used instead of resorting to transforms in the digital domain to extract time-frequency-phase signal components[^12]. The DDWS presents one approach to reduce hardware requirements for this type of measurement because it allows the direct extraction of a specific signal band but also appropriately decimates the output as each wavelet correlation yields a single result for that particular time-frame thereby reducing overall data rate.
{{< figure src="/images/biocas2018/concept.svg" title="Figure 1: Instrumentation system that extracts non-stationary frequency components from electrode recordings using wavelets that are generated by the proposed DDWS." width="500" >}}
The overall system architecture is shown in Fig. 1. This represents the front-end for a local-field-potential decoding system for BMIs[^13]. After amplification the electrode potential is mixed with two quadrature wavelets that have 50% overlapping time-frames. Similar to conventional spectroscopy[^6], the phase and amplitude can be recovered for each frame by evaluating the down-converted DC-component and will correspond to the frequency band set by the DDWS configuration. The DDWS will generate timing information for each frame that can be used to reset an analogue integrator that proceeds the mixing process and accurately extract the DC value. The proposed topology follows the principle of analogue-to-information conversion where the input signal is mixed linearly/non-linearly to maximally reduce the sampling speed of the data converter and optimise the spectral efficiency at the output. This alleviates the speed of signal conversion and digital processing. If the synthesis of these wavelets can be made highly resource efficient and programmable, several signal features can be directly extracted in the analogue domain by using multiple DDWS modules in parallel.
The rest of this paper if organised as follows: Sec 3 will introduce a recurrent digital oscillator core that forms the basis of the DDWS. Sec 4 describes the DDWS topology and Sec 5 presents synthesis data together with simulation results. Finally, Sec 6 will conclude this work.
# 3 A Feed-Forward Digital Oscillator Core
{{< figure src="/images/biocas2018/core.svg" title="Figure 2: Feed-forward digital oscillator showing the block diagram in (a) and the z-domain pole-zero plot of the feedback loop in (b) with decreasing k for a fixed frequency." width="500" >}}
There are a number of recursive oscillator topologies available in the literature with two identifiable basis; biquads and waveguides[^9]. The feed-forward structure proposed here is derived from the standard coupled quadrature structure that provides feedback with equi-amplitude quadrature outputs. This structure is shown in Fig. 2a. The feed-forward configuration uses two integrators in negative feedback with two coefficients f and k to specify frequency and Q-factor respectively. This will require the same number of coefficient multiplications as the coupled quadrature configuration but uses 4 2-input summation nodes opposed to 2. The benefit here is that there are only 2 scaling coefficients and they are linearly dependent on the desired oscillation frequency. The conventional structure has f²\:dependence that requires excessive integrator precision to accurately resolve very small frequencies typically of interest for biomedical signals.
$$ \begin{bmatrix}\hat{x}_Q \hat{x}_I\end{bmatrix} =\underbrace{\begin{bmatrix}(1-k f) & -f f & (1-k f)\end{bmatrix}}_{\mathbf{R}(k,f)}\cdot\begin{bmatrix}x_Q x_I\end{bmatrix} $$
Digital oscillators are usually characterised in terms of a rotation matrix \\(\mathbf{R}\\)(k,f) that is applied to two state variables x<sub>Q<sub> and x<sub>I<sub>. This representation is formulated in Eq. 1. For clarity the k²\: factor is ignored in this analysis since it yields a simpler solution to the basic feed-forward configuration. In this case we are interested in manipulating the pole location adaptively which is why we will solve for the complex pole positions of this dynamic system below.
$$ D_O(z) = f^2 \left(\frac{z^{-1}}{1-z^{-1}} \right)^2 + 2k f \frac{z^{-1}}{1-z^{-1}} $$
$$ denum\left(\frac{1}{1+D_O(z)}\right) = z^2 + (2 f k - 2)z + (f^2 - 2 f k + 1 ) $$
The z-domain representation of the open loop response D<sub>O<sub> is shown in Eq. 2 and the the corresponding expression for the denumerator of the closed loop response is shown in Eq. 3.
$$ \begin{split}poles\left(\frac{1}{1+D_O(z)}\right) = 1 - k f \pm √{ f^2 k^2 - f^2}\end{split} $$
Finding the poles yields the two solutions in Eq. 4 that correspond to the complex pair P\tss{Q/I} which dictate the oscillatory behaviour of this circuit. This reveals the behaviour shown in Fig. 2b which is that adjusting k will rotate the pole-pair in and out of the unit circle resulting in a growing or receding complex exponential or oscillation. It is also readily seen that for the case k=0 the pole locations lie outside the unit circle. Solving for a steady state solution where P\tss{Q/I} are on the unit circle gives k=f/2.
# 4 DDWS Core]{\\(\Delta\Sigma^2\\) type DDWS Core
In order to realise the proposed multiplier-free DDWS, two additional components will be introduced. The first is a second order digital ΔΣ \: modulator that will allow us to mitigate the need to for high-precision multipliers and the second is a controller module that will regulate the dynamic oscillatory behaviour given a set input parameters. This configuration is shown in Fig. 3 together with sub-blocks for amplitude tracking and noise shaping.
{{< figure src="/images/biocas2018/ddws-core.svg" title="Figure 3: Block diagram of the direct-digital wavelet synthesizer showing the system in (a), the amplitude tracking logic in (b) and the ΔΣ² \: modulator in (c)." width="500" >}}
Introducing a ΔΣ \: modulator is a well established means reduce hardware complexity for multiplication as the \\(\pm\\)1 single bit-stream implies that the coefficients (f & k) can be directly accumulated accordingly [^14]. This is particularly appropriate here because the typical clock speed will be at a substantially higher frequency than the signal bandwidth of interest. For biomedical systems these frequencies are almost always sub-10 kHz. Hence we can freely choose an oversampling ratio (OSR) according to our dynamic range requirement using DR=-11 dB+50 log(OSR)[^15].
The block diagram in Fig. 3 also includes logic for tracking the peak to peak amplitude of the internal oscillation. This is done by detecting zero-crossings of either integrator and latching the other that will at that moment be at the peak amplitude. The oscillation amplitude is used to control the dynamics of the wavelet generator and prevents saturation.
\begin{algorithm}
\DontPrintSemicolon
\KwIn{Wavelet synthesis parameters (f, c<sub>bw<sub>, ic, vpp)}
\KwResult{Quadrature bit-streams (D1\tss{Q/I}, D2\tss{Q/I})}
**Initialise:** x1<sub>Q<sub>=ic, x1<sub>I<sub>=0, x2<sub>Q<sub>=vpp/2, x2<sub>I<sub>=0, s1=c<sub>bw<sub>, s2=-c<sub>bw<sub>
\Begin{
\ShowLn
k1 = 0.5 + s1(D1<sub>PP<sub> - vpp)
k2 = 0.5 + s2(D2<sub>PP<sub> - vpp)
\\(\mathbf{x1}\\)\tss{Q/I}[n] = \\(\mathbf{R}\\)(k1,f) \\(\cdot\\) \\(\mathbf{x1}\\)\tss{Q/I}[n-1]
\\(\mathbf{x2}\\)\tss{Q/I}[n] = \\(\mathbf{R}\\)(k2,f) \\(\cdot\\) \\(\mathbf{x2}\\)\tss{Q/I}[n-1]
\uIf{ D1<sub>PP<sub> \textgreater vpp **or** $|\\(k1\\)|$ \textless c<sub>bw<sub>/2}{s1=-c<sub>bw<sub>}
\ElseIf{ D1<sub>PP<sub> \textless ic **and** s2\textless0 }{s1=c<sub>bw<sub>}
\uIf{ D2<sub>PP<sub> \textgreater vpp **or** $|\\(k2\\)|$ \textless c<sub>bw<sub>/2}{s2=-c<sub>bw<sub>}
\ElseIf{ D2<sub>PP<sub> \textless ic **and** s1\textless0 }{s2=c<sub>bw<sub>}
}
\BlankLine
\caption{DDWS Controller}
\label{algo:ddws-control}
\end{algorithm}
An overview of the control logic is described in Alg. 1. Here the notation from Eq. 1 is used to simplify how the oscillator states evolve by using the rotation matrix. In the behavioural implementation lines 5-6 are realised by a series of conditional statements that increment/decrement the oscillator states \\(\mathbf{x}\\)\tss{Q/I} and then compute the feed forward value by adding or subtracting k1/k2. Notice that we use the state variable s1/s2 to iteratively make sure only one oscillator is growing in amplitude while the other is shrinking in amplitude but at all times the growth is bounded by how close the peak to peak value is to the target maximum vpp. In fact several configurable parameters are used here in addition to vpp to specify the wavelet dynamics. Like before f controls the oscillation frequency in rads per second. The parameter ic determines the extinction ratio between the minimum and maximum oscillation amplitudes and c<sub>bw<sub> controls the window bandwidth together with ic to allow high or low out-of-band rejection.
Let us briefly identify the type of envelope modulation used here that allows these wavelets to perform time-frequency analysis. First it is important to point out that the phase state of each oscillator is not effected by small changes in k during operation. This means that the phase of the quadrature oscillator always accumulates with respect to the global reset. From our derivation in Sec 3 we can evaluate that, while s1/s2 does not change, the change in envelope can be expressed as Eq. 5 and which is resolved in Eq. 6 to show that the envelope has a sigmoid characteristic. In fact, As s1/s2 toggles the DDWS generates double sided sigmoid with a small discontinuity in the derivative the sinusoids that is proportional to c<sub>bw<sub>.
$$ \frac{dx(t)}{dt} = a x \cdot (b - x(t)) $$
$$ x(t) = \frac{b}{1+(b)e^{-a b x(t)}} $$
# 5 Implementation Results
A behavioural verilog model of the proposed wavelet generator has been implemented and synthesized using a low-power, small-footprint, LCMXO3LF FPGA device from Lattice Semiconductor and the Lattice Synthesis Engine (Version 3.10.2). The logic requirements and simulation results provide preliminary validation and can be further optimised given application constraints such as precision or resource limitations. The synthesis results are presented in Table 1 to show the relative hardware complexity for the 4-ΔΣ\: modulators, the two quadrature oscillators DX 1 & 2, and the top level FSM that controls the dynamics according to the input parameters. These requirements can be further compared using the pie chart in figure 4. Including the modulator hardware is useful if analogue requirements need to be relaxed to 1-bit digital-to-analogue conversion but this may not always be applicable. In fact, if a multi-bit output can be used instead, the modulators can be replaced by two multipliers to further optimise the resource requirements.
Table 1: Synthesis Summary
| Resource | LUT4 | Register | SLICE |
|----|----|----|----|
| FSM | 10 | 24 | 10 |
| DX \: (2x) | 5 | 217 | 125 |
| ΔΣ \: (4x) | 16 | 160 | 112 |
| DDWS Total | 31 | 401 | 252|
{{< figure src="/images/biocas2018/resource.svg" title="Figure 4: Resource distribution for the DDWS with the cost each sub-system annotated." width="500" >}}
Using a hypothetical configuration, the model was also simulated to demonstrate overall characteristics to filter out a specific 3.5 mHz normalised frequency band. The later implies that a 1.4 kHz system clock yields a 5 Hz center frequency. With reference to Algo \ref{algo:ddws-control} we used the following parameters: f=0.011, OSR=32, vpp=1, ic=2\\(^{-6}\\). In figure 5 c<sub>bw<sub>=2\\(^{-2}\\) and in figure 6 c<sub>bw<sub>=2\\(^{-6}\\) in order to show narrow and wide bandpass selection settings. Both figures show the time & frequency domain characteristics as well as the dynamic change in the pre-scaled feed-forward factor as the amplitude of oscillation increases before the controller changes state and starts suppressing the oscillation to near the end of the time window.
{{< figure src="/images/biocas2018/narrow.svg" title="Figure 5: Simulation result showing the transient output after decimation of the two quadrature bit-streams (top), the adaptive control of k (middle), and the frequency response of the generated wavelet. " width="500" >}}
{{< figure src="/images/biocas2018/wide.svg" title="Figure 6: Simulation result showing similar results as in figure 5 but with a smaller value of c<sub>bw<sub>." width="500" >}}
# 6 Conclusion
This work demonstrated a novel approach to generate wavelets using direct digital synthesis opposed to storing them in memory which is particularly useful for ultra-low-power medical devices that need to perform coherent time-resolved analysis of low frequencies. The synthesis results demonstrate that the dynamic approach avoids large memory requirements and digital complexity while retaining high precision frequency selection with reconfigurable bandwidths.
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