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---
title: "A 0.016 mm² 12 b ΔΣSAR With 14 fJ/conv. for Ultra Low Power Biosensor Arrays"
date: 2017-06-15T15:26:46+01:00
draft: false
toc: true
math: true
type: posts
tags:
- publication
- instrumentation
- CMOS
- biomedical
- data-converter
---
Lieuwe B. Leene, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
The instrumentation systems for implantable brain machine interfaces represent one of the most demanding applications for ultra low power analogue-to-digital-converters (ADC) to date. To address this challenge this paper proposes a \\(\Delta\Sigma\\)SAR topology for very large sensor arrays that allows an exceptional reduction in silicon footprint by using a continuous time 0-2 MASH topology. This configuration uses a specialized FIR window to decimate the \\(\Delta\Sigma\\) modulator output and reject mismatch errors from the SAR quantizer which mitigates the overhead from dynamic element matching techniques commonly used to achieve high precision.} A fully differential prototype was fabricated using \cmostech to demonstrate 10.8 ENOB precision with a 0.016 mm² silicon footprint. Moreover a 14 fJ/conv figure-of-merit (FOM) can be achieved while resolving signals with the maximum input amplitude of \\(\pm\\)1.2 Vpp sampled at 200 kS/s.} The ADC topology exhibits a number of promising characteristics for both high speed and ultra low power systems due to the reduced complexity, switching noise, sampling load, and oversampling ratio which are critical parameters for many sensor applications.
# 2 Introduction
The emergent market for wearable electronics and implantable devices for personalized health care has resulted in a growing demand for miniaturized battery powered systems that wirelessly connect a network of sensors[^1]. These systems rely extensively on high precision analogue to digital conversion to leverage digital processing techniques and accommodate stringent diagnostic requirements[^2]. As a result the ADC power, area, and precision can have a profound impact on a system's overall capabilities. For this reason oversampling techniques using \\(\Delta\Sigma\\) ADCs have already been used extensively to accommodate the niche characteristics of biomedical devices and acquire low frequency bio-signals [^3].}
More recent developments allow these techniques to be more applicable to large sensor arrays using an incremental analogue to digital converter (IADC) topology [^4]. This is in contrast to the conventional use where a single oversampling ADC continuously converts the signal from a single sensing unit with exceptional efficiency. IADC designs are unique in the sense that they periodically reset the loop filter which enables a single ADC to process multiple analogue inputs with reduced latency. This periodic reset associates a particular conversion time for each result and enables pipelined [^4], two-step [^5], or multi-step operation [^6]}. The resulting modulator can exhibit reduced mismatch sensitivity and require a smaller oversampling ratio while achieving equivalent performance to that of higher order modulators[^7]. This is crucial for larger sensor arrays because reduced circuit complexity leads to more compact designs and faster signal conversion. These earlier publications realize an IADC structure that explicitly transfers the quantization residue from one quantizer to the next using a sample and hold mechanism which is not necessarily required. For instance the zoom technique used in [^8] reuses the capacitive DAC during conversion thereby reducing complexity and power consumption. The resulting system achieves exceptional precision by combining a SAR with a second order switched capacitor (SC) \\(\Delta\Sigma\\) modulator. A common problem however is that the SAR INL/DNL errors are not shaped by the loop filter and end up limiting the overall precision unless dynamic element matching techniques (DEM) are used. This can lead to exhaustive digital overhead for DEM control and necessitate additional redundancy in the capacitive digital to analogue converter (DAC) to remove the SAR nonlinearity[^9].}
{{< figure src="/images/tcas2017/block_sys.svg" title="Figure 1: Block level implementation of the proposed ADC array structure for sensor arrays using SAR and \\(\Delta\Sigma\\) quantizers where a digital filter is applied to the comparator bit stream to perform decimation and mismatch correction." width="500" >}}
The system proposed by this paper is illustrated in Fig. 1 which uses a SAR and CT-\\(\Delta\Sigma\\) together to convert the signal from four analogue inputs. This configuration is then tiled 16 times in parallel to record from 64 channels simultaneously for neural recording applications. The topology is introduced as a $\Delta \Sigma$SAR because it emerged from introducing higher order CT-\\(\Delta\Sigma\\) type noise shaping to the SAR by processing the residue charge left after the SAR conversion. Using SC techniques with a similar motivation also lead to the noise shaping SAR (NSSAR) topology from [^10] which has been used extensively to achieve very high resolution SARs [^11] and higher order modulators with reduced active filter structures [^12]. In fact the fully-passive NSSAR technique can increase the SAR precision by several bits while immune to PVT variation [^13]. The distinction here is that the NSSAR will shape the quantization noise over multiple samples by introducing 1 to 3 extra cycles per sample where as the $\Delta \Sigma$SAR will allow one-shot conversions but introduce considerably more cycles corresponding to the oversampling ratio of the modulator. The later is characteristic of IADC operation. Additionally the CT approach leads to an inherent reduction in size because the loop filter is not subject to extra sources of sampling noise typical in CS circuits.} The IADC 0-2 multi-stage noise shaping (MASH) quantization scheme used by the \\(\Delta\Sigma\\)SAR can be interpreted as first resolving the sampled input using a conventional SAR and then applying a \\(\Delta\Sigma\\) feedback loop to resolve the remaining quantization residue left on the capacitor array equivalent to the zoom technique. The resulting bit stream from the comparator output consists of both SAR and oversampled quantization results. The advantage this topology presents is that it can be configured without the need for DEM or analogue dithering techniques because SAR INL/DNL errors can instead be cancelled by calibrating the FIR filter that processes this bit stream in the digital domain. This minimises capacitive switching during signal conversion and reduces overall complexity. Moreover by virtue of resolving a small SAR residue, the CT loop filter can maximize its noise efficiency without much concern for distortion or modulator nonlinearity.}
This paper presents an analytic design method for evaluating which condition allows the zoom type IADCs to exhibit high performance and which two-step configuration will lead to the best efficiency or size. Preliminary efforts to realize the system in Fig. 1 are presented in [^14] and the circuits proposed here are improved to achieve better power efficiency as part of a larger reconfigurable neural recording system [^15]. This system uses an array of miniaturised ADCs that distributes the digital processing over many parallel segments leading to lower clock frequencies and better efficiency opposed to demanding a single high frequency ADC and digital core.} To present the design characteristics of the \\(\Delta\Sigma\\)SAR, this paper is organized as follows. Section \ref{sec:design} introduces the principle design relations of this ADC structure with regard to system efficiency and size. This is followed by the proposed mismatch compensation method in Section \ref{sec:cali}. The circuit level implementation is proposed in Section \ref{sec:circ} with design considerations for the loop filter, capacitive DAC and FIR filter. Finally measured results are presented in Section \ref{sec:mes} which are used to draw conclusions in Section \ref{sec:con}.
# 3 \\(\Delta\Sigma\\)SAR Architecture
The \\(\Delta\Sigma\\)SAR topology closely resembles the SAR with an additional loop filter that can switch between amplifying \\(A(s)\\) and integrating \\(H(s)\\) behaviour following the last SAR conversion. This similarity is shown in Fig. 2 which represents a single ended equivalent of the fully differential implementation described here. The input signal is sampled on the bottom plate of the capacitive array such that conventional SAR feedback can be applied while the loop filter is initially providing wideband amplification of 10x. Once the first \\(N\\) bits are resolved the comparator output is connected directly to a unit element in the capacitive array for the \\(\Delta\Sigma\\) quantization phase. Simultaneously the loop filter is switched to introduce second order noise shaping and resolves another \\(M\\) bits using DC extra oversampling cycles. In theory this will result in \\(M+N\\) bits of precision but in practice the SAR conversion will need to evaluate \\(N+1\\) bits with 1 bit of redundancy. This redundancy implies that the residue will always be half of the modulator input range to prevent overloading the \\(\Delta\Sigma\\) ADC[^16]. If 1 cycle is used for sampling the ADC will need to be clocked at \\((N+DC+2)f_{smp}\\) for a sampling frequency \\(f_{smp}\\) with a modulator bandwidth \\(f_{bw}\\) at half this clock frequency. A typical conversion is illustrated by the timing diagram in Fig. 3 which shows the FSM using 1 cycle for sampling, \\(N+1\\) cycles for SAR, and DC cycles for \\(\Delta\Sigma\\) modulation. Meanwhile the comparator results will infer if the corresponding FIR coefficient provided by a shared controller is added or subtracted from a local accumulator thereby resolving the input signal. To provide insight to the design considerations we will first discuss the noise requirements needed for achieving a \\(N+M\\) ADC precision. This will reveal the dominant power requirements due to the filter and capacitive DAC and also give some indication about the size of each capacitor in Fig. 2 which can then be used to estimate area. Note however that the defining characteristic of this quantization process is that the SAR residue is bound to a well defined voltage range of $\pm V_{R}/2^{N+1}$ where \\(V_{R}\\) is the ADC reference voltage. The reduced input range implies that feedback may not be needed to linearise the Gm-C loop filter used during \\(\Delta\Sigma\\) conversion but it also indicates the filter coefficients have to be carefully adjusted to achieve second order noise shaping. }
{{< figure src="/images/tcas2017/sch_adc.svg" title="Figure 2: Proposed topology that interoperates SAR and oversampling quantizers in the same signal loop using a capacitive DAC, switched loop filter, and single bit quantizer." width="500" >}}
{{< figure src="/images/tcas2017/fsm.svg" title="Figure 3: Timing diagram of the sampling (SMP), SAR (S0-SN), and oversampling (\\(\Delta\Sigma\\)) modes of operation where \\(C_{0}\\) to \\(C_{N+DC}\\) correspond to the calibrated coefficients of the FIR filter. EOC is the end-of-conversion signal that is put low when the quantization process is finished. " width="500" >}}
## 4 Topology Optimization
The efficient operation of low speed ADCs primarily relies on the careful consideration of various noise sources to avoid dissipating excess power. However the two modes of operation have characteristically different requirements. Concisely stated the \\(\Delta\Sigma\\) modulator will focus on achieving a specific noise floor because out of band noise is removed after decimation while the SAR operation is sensitive to integrated noise over the entire circuit bandwidth. To illustrate the design relations quantitatively the following discussion will reiterate on several expressions from well established \\(\Delta\Sigma\\) theory [^17]. This will allow us to determine system constraints particularly with respect to the analogue filter that provides second order noise shaping and in this case consumes most of the power.}
## 5 Filter Noise Constraints
First recall that the oversampling ratio for a second order modulator is dictated by Eq. 1 in terms of resolving \\(M\\) bits. This will later be used in association with the expression in Eq. 2 to evaluate acceptable quantization noise power \\(S^2_{n}\\) for a \\(N+M\\) precision ADC.}
$$ DC \geq \sqrt[5]{ \frac{2 \pi^4}{15 \cdot 2^{-2(M+1)}}} $$
$$ S^2_{n} =\frac{1}{12} \left( \frac{V_R}{2^{N+M+1}} \right)^2 $$
Now in order to capture the subjective performance of the circuit level implementation and its impact, this analysis uses the Noise Efficiency Factor (NEF). The expression for NEF in Eq. 3 normalizes the input referred noise \\(e^2_{in}\\) of a particular implementation to that of a bipolar transistor with a biasing current equivalent to that used by the filter \\(I_{filt}\\). As a result we can abstractly consider noise-power relations without considering a specific filter topology that will exhibit some particular NEF.}
$$ NEF^2 \deff \frac{2 I_{filt} e^2_{in}}{\pi U_T 4kT f_{bw}} $$
In fact by combining this with the ADC noise requirement in Eq. 2, \\(I_{filt}\\) can be predicted as a function of circuit topology and its equivalent NEF. This is detailed in Eq. 4 under the condition that \\(e^2_{in} = S^2_{n}\\) where the relevant circuit noise bandwidth is reduced \\(f_{bw}/DC\\) due to oversampling.}
$$ I_{filt} = \pi U_T 24kT \frac{ f_{bw} }{ DC } \left( \frac{ 2^{N+M+1} NEF }{V_R} \right)^2 $$
Similarly \\(I_{filt}\\) can be evaluated for just the SAR operation as a special case: $I_{SAR} \deff I_{filt}(DC=1,M=0)$. In the case that \\(I_{SAR}\\) is larger than the estimate in Eq. 4 we should adopt that value instead. This result is mainly relevant for SAR converters where an analogue amplifier is used to precede the comparator and thereby dominating the noise requirements[^18]. Here it will also be used to indicate the preliminary performance with respect to \\(N\\) & \\(M\\) with a fixed clock speed and the associated conversion time of \\(N+DC+2\\) cycles. The resulting conversion efficiency is proportional to \\(2^{N+M}/P_A(N+DC+2)\\) as conversion per Watt where total analogue power is estimated as $P_{A} \approx V_{R}I_{filt}$. In this case the filter supply voltage is simply equal to the reference voltage. Normalization allows the relative efficiency to be visualized in Fig. 4 which provides some evidence that the filter alone tends to be more efficient as \\(M\\) becomes larger than \\(N\\). However \\(N\\) can not be arbitrarily small if the residue need to be kept in the linear range of the modulator. This implies a direct relationship between the ADC reference voltage and the minimum SAR resolution.} The details of this requirement is strongly dependent on the full ADC precision and its sensitivity towards transistor nonlinearity. However as a priori the minimum SAR resolution \\(N\\) can be approximated by considering that the linear input range for a sub-threshold differential input pair is related to the thermal voltage $\pm U_{T}$[^19] which suggests that \\(N \geq\log_2(V_{R}/U_{T})\\) to keep the residue inside the linear range.}
{{< figure src="/images/tcas2017/Cost.svg" title="Figure 4: Power efficiency as \\(2^{N+M}/P_A(N+DC+2)\\) in terms of conversions per Watt where \\(N+M\\) is the target precision of the analogue filter for different values of \\(N\\) & \\(M\\) normalised by the best case where \\(M=8\\) & \\(N=1\\).}" width="500" >}}
## 6 Estimating System Power
The previous result is relatively optimistic in the sense that it does not consider the decimation filter or DAC power dissipation. To warrant an accurate estimation of the ADC's efficiency and resource requirements the Digital \\(P_{D}\\), and capacitive switching \\(P_{C}\\) losses should also be estimated.}
$$ P_C = C_{U} f_{smp} V^2_R \left(DC/2 + \sum_{i=1}^{N} (2^i-1) 2^{N-2i-2} \right) $$
Eq. 5 includes the SAR energy dissipation in terms of the capacitive switching using the analysis from [^20].} The \\(V_{cm}\\) based switching method employed here retains a stable common mode on \\(V_{DAC}\\) with good conversion efficiency. This will help to preserve the linearity of the modulator. Variation in common mode voltage changes the offset of the loop filter as well as the impact of top plate parasitics[^20]. Both will introduce nonlinearity that is convoluted by the SAR quantization process and can be challenging to compensate accurately. \\(P_{C}\\) is evaluated for \\(N+1\\) SAR cycles where the unit capacitor \\(C_{U}\\) size introduces some degree of freedom. Strictly the total capacitance is bounded such that the \\(kT/C\\) noise is smaller than noise requirement of Eq. 2. For instance we could let the sampling noise contribute half the allowable noise power which leads to a minimum capacitance according to Eq. 6 given a \\(2^{N+1}\\) unit binary DAC.
$$ C_U = \frac{12 kT}{V_R^2} 2^{N+2M+1} $$
This unit element should be noticeably larger than what may be expected from SAR configurations due to the small number of elements in the capacitor array resulting in reduced matching and interconnect complexity. Generally such a configuration will favour high density vertical metal-insulator-metal (MIM) capacitors that have large minimum size requirements and can be placed over active circuitry to reduce silicon footprint. In fact by using a split capacitor configuration the size of \\(C_{U}\\) can be even larger with less elements in the array for the same sampling capacitance leading to very efficient utilization of MIM capacitor area[^21]. It may still be the case that \\(C_{U}\\) is smaller than the minimum capacitance \\(C_{min}\\) for intermediate precision of 6-10 bits. In such a case this model will simply adopt \\(C_{min}\\). This will also apply to the load capacitance \\(C_{L1}\\) when it is calculated with respect to the modulator bandwidth as \\(f_{bw}=gm_{1}/C_{L1}\\). However this should carefully consider the reduced input swing of \\(V_{R}/2^{N+1}\\) which means the transconductance for a conventional fully-differential input in sub-threshold operation would be $gm_{1}=V_{R} I_{filt}/(\eta U_{T} 2^{N})$ where \\(\eta\\) is the transistor slope factor.
In order to estimate the digital losses this model extrapolates the energy dissipation per clock cycle extracted from a 1 bit accumulator taken as \\(E_{reg}\\). The associated register depth \\(R_{D}=N+M+log_{2}(DC)\\) bits is derived by considering the accumulated rounding errors from DC additions during FIR decimation}. This leads to Eq. 7 which is expected to be insignificant at higher resolutions because decimation filter has reduced requirements when compared to the full precision of the integrator.
$$ P_D = R_D E_{reg} f_{smp} \underbrace{(DC+N+2)}_{Cycles/Sample} $$
## 7 FOM Dependence
The above relations should provide a good indication for the power requirements even though some system components such as the comparator and auxiliary circuits have been ignored. The Walden \\(FOM_{W}\\) and Schreier \\(FOM_{S}\\) are presented in Eq. 8 & 9. These performance metrics are plotted in Fig. 5 by assuming typical values from the \cmostech process. \\(V_{R}\\) is adjusted to \\(0.6/1.2/2.4 V\\) which keeps the linear input range of the \\(\Delta\Sigma\\) modulator consistent while resolving different SAR resolutions for fair comparison. Other constants are assumed as follows; \\(\eta=1.2\\), \\(NEF=1.4\\), \\(E_{reg}=1\\) fJ, \\(C_{min}=10\\) fF, \\(f_{smp}=10^5\\) Hz, \\(f_{bw}=10^5 (N+DC+2)/2\\) Hz. The general trend presented here is that the topology operates at maximal performance when the most of the power is dissipated by the oversampling loop and the lowest energy per conversion is dissipated when the capacitive switching and modulator power become comparable. It is not surprising that reducing the supply voltage makes it more difficult to achieve a good FOM because the absolute noise performance becomes more difficult to achieve. For reference a conventional $\Delta \Sigma$ modulator [^22] is designed with the same target specifications and using the same analysis method to configure the OPAMP integrators and resistive input network. Such a configuration achieves 167 dB \\(FOM_{S}\\) irrespective of target resolution when we consider just the filter power dissipation. In fact this figure is commonly achieved by state of the art [^8]. This highlights how the \\(\Delta\Sigma\\)SAR configuration can theoretically achieve more than 2X better performance for resolutions above 12 bits even when operating at lower supply voltages.
$$ FOM_W = \frac{P_C + P_D + P_A}{f_{smp} 2^{N+M}} $$
$$ FOM_S = 6.02 (N+M) + 10 \log_{10}\left( \frac{f_{smp}/2}{P_C + P_D + P_A}\right) $$
{{< figure src="/images/tcas2017/AMD.svg" title="Figure 5: Estimation on the expected \\(FOM_{S}\\) and \\(FOM_{W}\\) for a resolution and varying SAR precision. The red star and blue circle indicate the target and measured performance respectively. The blue stars correspond to \\(FOM_{W}\\) achieved by other works." width="500" >}}
{{< figure src="/images/tcas2017/APM.svg" title="Figure 6: Estimated area requirements with respect to ADC resolution for various SAR resolutions. The red star and blue circle indicate the target and measured performance respectively. The blue stars correspond to area achieved by other works." width="500" >}}
{{< figure src="/images/tcas2017/FOMS_EA.svg" title="Figure 7: The estimated DOP with respect to the target ENOB and the \\(\Delta\Sigma\\) modulator resolution. This normalised by the best configuration where \\(M=5.8\\) & \\(ENOB=10.9\\) (i.e. \\(N=5.1\\)). \\(V_{R}\\) is assumed to be 1.2 V and the red star indicates the target performance for this implementation.}" width="500" >}}
$$ EA = \left( 2 C_{L1} + C_{U} 2^{N+2} \right) / C_{dens} $$
The required area for this configuration is estimated by Eq. 10 which uses the MIM capacitor density \\(C_{dens}\\) of 2fF/\mmu m². As shown in Fig. 6 high resolution configurations will tend towards noise limited requirements that are closely related to the integration and sampling capacitors. Lower resolutions are largely dependent on technology and how the SAR DAC is configured to address mismatch. Fig. 7 shows the impact of \\(M\\) on overall ADC efficiency in combination with the area requirement. This is characterised using the density of performance $DOP = FOM_{S}-10 log_{10}(EA)$ which peaks for an ENOB of 11.4 bits with \\(M\\) being 5.8 bits.} The overall quantitative results show exceptional figures of merit with highly compact configurations for 10-16 bit designs from first principles. The design described above only focuses on achieving an optimal noise performance because it dominates the low frequency FOM metrics.} Naturally a number of extra considerations need to be made for achieving the desired ENOB. Finding the requirements for open loop gain, parasitics, nonlinearity, and digital filtering is done by using numerical optimization on simplified models guided by analytic results from prior work [^22][^24]. However we can observe some agreement with this simplified model and the performance achieved in other works.}
# 8 Foreground Calibration for the $\Delta \Sigma$SAR
{{< figure src="/images/tcas2017/cal_tran.svg" title="Figure 8: Simplified model of the ADC structure quantization process illustrating how capacitor weight estimation \\(W_{SAR}\\) and actual capacitor weights \\(W_{DAC}\\) propagate to the output.}" width="500" >}}
The foregoing analysis suggests that the resources dedicated to SAR operation should be kept small in order to achieve the peak performance of the oversampling modulator. As a result the DAC linearity may be much worse than the target precision. Ideally before instrumentation the system should perform a calibration procedure that determines the actual capacitor weights \\(\mathbf{W}_{DAC}\\) and recovers any lost accuracy due to mismatch in the digital domain[^26][^25]. Digital calibration techniques are extensively used for SAR converters because they enable more aggressive capacitor sizing without introducing extra analogue complexity that does not benefit from technology scaling[^27]. A simplified model of the quantization process is shown in Fig. 8 where the SAR result is fed back according to the 7 capacitor weights \\(\mathbf{W}_{DAC}\\) to produce a residue that is oversampled by the modulator and decimated by the FIR filter. The mismatch errors arise when the coefficients \\(\mathbf{W}_{SAR}\\) do not correctly calculate the exact charge offset by the capacitors (i.e. $\mathbf{W}_{DAC} \neq \mathbf{W}_{SAR}$). The structural advantage here is that all mismatch induced errors are accurately evaluated by the oversampling loop which can operate with extra noise shaping during calibration without needing a more precise reference ADC. First note that the DNL errors due to DAC mismatch are only observed upon changes in the SAR codes. Secondly the single bit \\(\Delta\Sigma\\) modulator can present significantly better linearity without calibration if SAR codes remain unchanged. Moreover if the weights are correctly estimated we should expect no discontinuities in the DNL characteristic for slowly varying inputs. The proposed calibration method takes advantage of these observations by correlating the first order difference of the ADC output and the SAR codes to find the correct coefficients for \\(\mathbf{W}_{SAR}\\). In addition by using a triangular test signal to perform calibration this procedure does not need full precision multipliers. This is because the triangular waveform distributes the occurrences of each SAR code evenly when at least one sample is taken per SAR code. Therefore the number of toggles on each SAR bit is exactly distributed as powers of two. Now if each SAR coefficient is adjusted when the respective SAR bit toggles then the rate of adjustment for each capacitor weight will be uniform if the adjustments are proportionally scaled by powers of two.}
$$ \mathbf{W}_{SAR}[n+1] = \mathbf{W}_{SAR}[n] + \boldsymbol{\alpha} \underbrace{ sign(\dot{Q_{out}}[n] \dot{\mathbf{Q}_{SAR}}[n])}_{\text{ternary result (+1/0/-1) } } $$
Eq. 11 introduces the proposed method for iteratively updating \\(\mathbf{W}_{SAR}\\) for the n\textsuperscript{th} sample using \\(\alpha\\) as fixed adjustment factor. \\(\dot{Q_{out}}\\) is the first order difference of the quantized output which is a function of the SAR \\(Q_{SAR}\\) and modulator \\(Q_{\Sigma\Delta}\\) outputs. The exact relation is expressed in Eq. 12. No multiplication is required here because whether a SAR bit has toggled is strictly Boolean and represented by \\(\dot{\mathbf{Q}_{SAR}}[n]\\). This leads to a ternary result with respect to the adjustment rule for incrementing or decrementing the estimated weights that can be implemented using 7 up/down counters of varying depth. In this case the MSB counter has a logical depth of 16 bits while the LSB uses 22 bits.}
$$ Q_{out}[n] = \mathbf{Q}_{SAR}[n] \cdot \mathbf{W}_{SAR}[n] + 2^{-N} \mathbf{Q}_{\Sigma\Delta} \cdot\mathbf{W}_{FIR} $$
If we presume our \\(\Delta\Sigma\\) converter has ideal performance then $2^{-N} \mathbf{Q}_{\Sigma\Delta} \cdot\mathbf{W}_{FIR} = V_{IN}[n] - \mathbf{W}_{DAC}[n]$ which leads to \\(\dot{Q_{out}}\\) as:}
$$ \dot{Q_{out}}[n] = \dot{V_{IN}[n]} + \dot{\mathbf{W}_{SAR}[n]} - \dot{\mathbf{W}_{DAC}[n]} $$
Eq. 13 reveals that during calibration the output will consist of two components. The first is due to the input as the ramp's rate of change \\(\dot{V_{IN}}\\) that is either increasing or decreasing. The second term results from an incorrect weight estimate on whichever SAR bit changed.} In fact depending on the sign of this error we know if the estimated weight needs to be larger or smaller. In essence Eq. 11 uniformly averages over all DNL errors to approach the correct weights.
# 9 Circuit Implementation
Using the foregoing results, the presented implementation targets a 12 bit resolution using \\(N=6\\) & \\(M=6\\) which should lie just on the inflection point of estimated area requirement curve. In particular we will present the configuration for a fully differential sensor array using analogue and digital supplies at 1.2 V and a commercially available 6-Metal \cmostech technology (AMS/IBM C18A6/7SF).}
## 10 Loop Filter
The loop filter topology used here is a second order feed forward architecture that is used extensively in CT modulators due to its reduced complexity and low distortion[^29][^28]. This particular structure reduces the number of summation nodes and digital feedback elements to minimise power consumption. The signal and noise transfer functions due the loop filter \\(H(s)=2^N (s^2+2 \omega_{bw} s)/\omega^2_{bw}\\) and the feedback factor $f\approx 2^{-N}$ are summarised in Eq. 14 & 15 where \\(\omega_{bw}\\) is the filter bandwidth in radians. The feedback \\(f\\) is determined by evaluating the capacitive coupling from \\(C_{\Delta\Sigma}\\) onto \\(V_{DAC}\\). Since \\(f\\) is quite small there is an apparent gain in the STF but not in the NTF. This gain is provided by increasing the bandwidth of the first stage by \\(2^{N}\\) which substantially diminishes the input referred noise from the second integrator and comparator.} Then using the requirements from Sec. 5 will allow the capacitors to be specified for this implementation as $f_{smp} (N+DC+2)/2=4V_{R} I_{B1}/(\eta U_{T} 2^{N} C_{L1})=2V_{R} I_{B2}/(\eta U_{T} C_{L2})$.}
$$ NTF(s) = \frac{s^2}{s^2 + 2 \omega_{bw} s + \omega^2_{bw}} $$
$$ STF(s) = 2^{N}\frac{2 \omega_{bw} s + \omega^2_{bw}}{s^2 + 2 \omega_{bw} s + \omega^2_{bw}} $$
{{< figure src="/images/tcas2017/sch_lf.svg" title="Figure 9: Schematic level implementation of the switched loop filter using noise efficient complementary transconductors and a current mode summation circuit." width="500" >}}
The transistor level implementation is shown in Fig. 9 where the switches \\(S_{\Delta\Sigma}\\) allow the filter to change its operation. The first stage uses a fully differential complementary or inverter-based transconductor that can tolerate small variations in input common mode fluctuation by \\(\pm\\)100 mV and this specific configuration exhibits an \\(NEF\approx1.6\\). The sizing of this complementary pair requires some attention regarding the capacitive loading on \\(V_{DAC}\\) due to the gate to drain capacitance of the transistors. In fact \\(C_{u}\\) needs to be considerably larger than this parasitic such that the open loop gain of the first integrator is not reduced and thereby diminishing filter performance.} The circuit is segmented into three sections; two analogue integrators and one summation stage. The first integrator will switch between resistive and capacitive loads. This stage will have the most demanding bandwidth requirement when providing pre-amplification during SAR quantization. Both integration capacitors are reset outside of the $\Delta \Sigma$ phase and the last two stages should achieve -40 dB HD<sub>3<sub> for a \\(\pm\\)100 mV input signal which is derived from simulations [^24]. The common mode feedback on the two integrators uses linear mode devices that reference \\(V_{DD}/2\\). These transistors can be quite large and introduce considerable parasitics because of the large current dissipated in the first stage. To avoid a reduction in bandwidth, a sub-set of these gates are connected to the loading capacitor \\(C_{L1}\\) that is switched out during SAR conversion which retains the steady state common mode voltage.} The 1-bit quantization is realized using a dynamic latch where offset associated concerns should follow conventional wisdom for accurate SAR conversion. The diode connected load in the summing stage places the input common mode of the comparator close to \\(V_{DD}\\). This improves both the bandwidth and noise performance of the latch[^30].}
## 11 Capacitive DAC
A 7-bit fully differential binary weighted capacitive DAC is used to perform the SAR quantization. The single ended structure is shown in Fig. 10. The voltage scaling on the last conversion cycle reduces the number of capacitors needed and takes advantage of the reduced reference sensitivity for the last SAR conversion. Because calibration is performed with respect to \\(C_{\Delta\Sigma}\\) that references \\(V_{R}\\) the mismatch in the last SAR coefficient will also accommodate the mismatch in voltage reference.} The array is realized by precision top metal-on-metal capacitor devices which utilize M5-M6. A M4 \\(V_{CM}\\) shield is introduced to isolate this array from active analogue and digital circuitry placed below. While bottom plate sampling diminishes the effect of parasitics on \\(V_{DAC}\\), the split capacitor needs tuning according to the extracted parasitics on the LSB section particularly with respect to the shielding layer. The unit capacitor is 71 fF with 6\\(\times\\)6 \mmu m\\(^2\\) dimensions yielding 0.2% deviation of capacitor mismatch for a \\(3\sigma\\) confidence interval. This should allow a precision of 9 ENOB without calibration [^31] and will utilise all the top metal area needed for the sub-blocks placed below.
{{< figure src="/images/tcas2017/sch_dac.svg" title="Figure 10: Single ended equivalent of the 7-bit split-capacitive SAR DAC using voltage scaling on the smallest weight. " width="500" >}}
During sampling each input will be loaded by a total of 768 fF for an equivalent 52 \mmu V<sub>rms<sub> sampling noise. This should indicate that the upper bound of maximum signal to noise and distortion ratio (SNDR) for this DAC is 78 dB. Also note that the INL characteristic of the SAR and comparator noise will inevitably lead to additional sources of quantization error which implies the \\(\Delta\Sigma\\) input range will correspondingly increase from its expected value. Moreover resolving a sampled input with a \\(\Delta\Sigma\\) modulator can lead to increased distortion due to idle tones. This is why the modulator should be designed such that signals that are -3 dB of the maximum \\(\Delta\Sigma\\) input range can still be adequately resolved. Fortunately comparing single bit modulators reveals second order feed-forward structures are substantially more capable of processing signals close to the full range input due to improved stability dynamics [^16]. This means the DAC mismatch requirements are less stringent and will not need a sub-binary weighting or additional calibration capacitors to minimize the sources of excess residue.} The simpler binary weighted structure will allow good baseline matching for the unit capacitors with the minimum number of elements in the DAC. Moreover introducing the split capacitor in addition to the \\(V_{cm}\\) switching method dramatically reduces the total switching energy to the extent that it is dominated by the oversampling phase. Particularly when multiple data converters are operated in parallel the excessive capacitive switching raises a concern for high frequency supply noise of the reference voltage that is outside the LDO bandwidth. The anti-aliasing provided by the loop filter will partly reject this component as a result of opting for a CT implementation. The \\(\Delta\Sigma\\) feedback will dissipate at most 77 fC every cycle which needs to be partly absorbed by decoupling capacitors local to the ADC. High density MOS capacitors are therefore introduced to load the reference voltage by 20 pF per ADC. The reduced switching noise should represent a clear advantage over switched capacitor modulators. An improvement over the conventional SAR may only be expected when calibration overhead is unavoidable because the sampling noise constraint makes energy dissipation in SAR switching mostly indifferent to its resolution.
## 12 FIR Filtering
Decimation of the \\(\Delta\Sigma\\) bit stream of incremental topologies finds the application of FIR filters particularly suitable. This is in part because resetting the integrators for each sample and discards residual components from the previous conversion and the corresponding group delay requirement can limit the IIR filter design.} Moreover sharing FIR filter coefficients with multiple ADCs reduces the hardware requirements to a shared lookup table with individual accumulators for each modulator. Using an \\(OSR\\) of 24 implies \\(N+DC+1=31\\) additions are needed per sample where a second order CIC filter would need at least \\(N+2DC+3=57\\) additions per sample for a full evaluation and four times the number of registers[^32]. From Sec. \ref{sec:model} we know that the register depth \\(R_{D}\\) should be 16 bits while the FIR coefficient precision needs to be 8 bits.} The application of a symmetric FIR window also assists with a number of circuit considerations for rejecting noisy aggressors near \\(f_{bw}\\)[^8]. Supply noise is a typical culprit but it may be less obvious that the FIR also reduces the sensitivity due to the second integrator's offset when the quantization mode switched.} Hanning or raised cosine FIR windows are known to provide exceptional aliasing particularly when applied to sample limited \\(\Delta\Sigma\\) decimation [^33]. Using a general family of raised cosine windows[^34] a configuration is proposed here that matches the noise shaping of the loop filter order (\\(L\\)) with that of the FIR side-lobe roll-off by defining its coefficients as:}
$$ FIR[n] = cos^{K}\left(\frac{\pi n}{OSR+1}-\frac{\pi}{2}\right) $$
The factor \\(K\\) in Eq. 16 determines the spectral characteristics of the filter similar to that of the kaiser windows. The rapid side-lobe roll-off is related to \\(K\\) as \\(30K \\)dB/Dec with the first zero location at \\(\pi(1+K/2) f_{smp}\\). Because the quantization noise is shaped in relation to \\(L\\) at \\(20L \\)dB/Dec[^5], \\(K\\) can be defined as \\(K=2/3 L\\). This leads to a near uniform quantization noise profile with a reduced transition band from better pole placement. The \\(K\\)-factor dependent frequency characteristics are shown in Fig. 11 for an \\(OSR=16\\) applied to the output of a second order modulator. Note that when \\(K=2\\) the FIR is equivalent to that of a Hanning window. The overall system transfer function \\(Sys(z)\\) can be analysed in the z-domain using a bilinear transform of the loop filter \\(H(s)\\) and convolving it with that of the FIR response. To see how well decimation is achieved we compare the decimation performance to that of an ideal filter .}
{{< figure src="/images/tcas2017/QFIR.svg" title="Figure 11: Overall noise shaping profile of the modulator and FIR in cascade for \\(K=2\\) and \\(K=1.33\\)." width="500" >}}
$$ S_Q^2 = \frac{ 2\pi^{2L} }{3(2L+1)(OSR)^{2L+1} } $$
Eq. 17 introduces the expected in-band quantization noise power \\(S_Q^2\\) from analytic relations[^35] which assume an ideal brick-wall filter with a cut off frequency at \\(f_{smp}/2\\) that is not limited in any way.} Similarly integrating over the resulting power densities in \\(Sys(z)\\) will indicate the expected quantization noise from the proposed configuration. Comparing these two results will indicate how effectively the quantization noise is rejected by the FIR filter.} The noise excess is shown in Fig. 12 as a function of OSR and filter order. This shows that using the proposed window results in loss smaller than 0.5 bits.} Also notice that we do not pay special attention to how the \\(\Delta\Sigma\\) quantization noise folds onto the signal band. After the signal is convolved by the SAR quantization process the residue no longer shares the same structure as the input signal and therefore better in band decimation performance will not lead to better in band SNR.}
{{< figure src="/images/tcas2017/OBT.svg" title="Figure 12: Quantization noise suppression based on numerical simulations and Eq. 17 and the respective precision loss for varying \\(OSR\\)." width="500" >}}
# 13 Measured Results
{{< figure src="/images/tcas2017/chip_micro.svg" title="Figure 13: Microphotograph of the 64 channel neural recording system showing two 32 channel macros used in parallel with integrated power management and digital processing.}" width="500" >}}
{{< figure src="/images/tcas2017/fab_exhibit.svg" title="Figure 14: Fabricated \\(\Delta\Sigma\\)SAR prototype showing a) an isolated test ADC structure used for characterization b) a close up micrograph showing the capacitive DAC and top metal c) the ADC layout with annotated sub-blocks. The SAR capacitors are highlighted in blue and numbered in term of which SAR bit they represent. The analogue MOS and MIM capacitors are highlighted in red showing the filter capacitors L1 & L2 and the decoupling capacitors.}" width="500" >}}
A chip micrograph is shown in Fig. 13 depicting the 64 channel instrumentation system with die size of 6.2 mm<sup>2<sup>. This configuration uses two macros each of which integrates eight ADCs together with the DSP in a tiled fashion to post-process the recordings from 32 instrumentation amplifiers. In fact the architecture may be scaled to accommodate more channels by virtue of the pipelined architecture that distributes the processing capacity. The measured results presented here are taken from an isolated test structure that allows detailed characterization without overhead from the whole system.} The physical implementation of the \\(\Delta\Sigma\\)SAR sub-block is shown in Fig. 14 which is 96\mmu m\\(\times\\) 164\mmu m in size. Because the DSP is assisted by a specialized execution unit that also performs neural signal decomposition only the digital accumulator is included in this figure. The active components inside the modulator contribute to a small portion to the overall system. Instead the most demanding layout consideration is with regard to the switches driving the capacitive DAC. Even though the capacitance is not too large, the switch resistance in \\(\Delta\Sigma\\) mode can introduce a pole leading to excess loop delay that could result in performance degradation [^36].
{{< figure src="/images/tcas2017/INL2.svg" title="Figure 15: Measured INL of the ADC before and after calibration with 2.4 V differential amplitude. " width="500" >}}
{{< figure src="/images/tcas2017/CALC.svg" title="Figure 16: Convergence of DNL rms and peak to peak values during calibration subject to a 90 Hz triangular waveform." width="500" >}}
Initial ADC characterization used a low-frequency 180 Hz tone at half to the full input range where the comparator bit stream was directly acquired off-chip for post-processing. This allowed the proposed calibration mechanism to be compared with more robust methods. In fact when using more elaborate numerical optimization methods to adjust \\(\mathbf{W}_{SAR}\\) the THD only showed 2 dB improvement although convergence is typically much faster. Both testing and calibration waveforms were generated off-chip using an Agilent 33120a with additional bandpass filtering. The measured INL characteristics are shown in Fig. 15. The calibration method decreases the SAR nonlinearity by a factor of 10. As shown in Fig. 16 the main drawback of this method is that in order to reject noisy perturbations the \\(\alpha\\) rate must be small amounting to slow convergence on the order of 10<sup>6<sup> quantization cycles or around 10 seconds. The DAC used for generating the ramp signal will need to be more accurate than the ADC precision to allow correct calibration. On the other hand instead of using a more powerful centralized DSP unit to perform tuning, this system allows all channels to calibrate simultaneously resulting in a speed up for multichannel systems that can share a single high resolution DAC.} The discontinuities visible in this trend result from the fitting method used to calculate DNL as a function of time which is not very consistent.
{{< figure src="/images/tcas2017/Spectrum2.svg" title="Figure 17: Measured ADC performance showing the spectral characteristics of a) SAR residue at the output of the \\(\Delta\Sigma\\) and b) the full precision output which has a SNDR of 66.8 dB. This recording was taken using a 2.35 Vpp 95 kHz input tone sampled at 200 kHz .}" width="500" >}}
{{< figure src="/images/tcas2017/QRES.svg" title="Figure 18: FIR output over time due to a 1.2 Vpp 180 Hz input tone showing the quantized residue after SAR conversion. " width="500" >}}
{{< figure src="/images/tcas2017/MMO.svg" title="Figure 19: Measured quantization noise spectrum of the second order \\(\Delta\Sigma\\) modulator that is clocked at 7 MHz averaged over 10<sup>3<sup> conversions with an OSR of 24.}" width="500" >}}
Fig. 17 shows the spectral characteristics of the ADC after the capacitor weights have been estimated with 16 bit precision together with the SAR residue that can be obtained by only taking the decimated modulator output. This illustrates that SAR residue has its spectral power distributed over the entire bandwidth at multiple tones. This wideband quantization 'noise' will in effect present dithering on modulator's nonlinearity before appearing at the output.} Fig. 18 shows the signal resolved by the modulator as a function of time. Interestingly the polarity in residue will directly correspond to the polarity of the sampled input signal because swapping the reference voltage on the capacitive DAC will imply a successive approximation while maintaining correspondingly positive or negative residues. Then by performing a Fourier transform on the measured modulator output for each conversion separately we can evaluate the noise shaping characteristic of the loop filter. This result is shown in Fig. 19 which follows closely to the expected second order noise shaping.}
{{< figure src="/images/tcas2017/SDOS.svg" title="Figure 20: Measured \\(FOM_{S}\\) dependency for varying OSRs but keeping a 7 MHz system clock frequency for a 10\\( kHz\\) 2.4 Vpp input tone." width="500" >}}
{{< figure src="/images/tcas2017/FDP.svg" title="Figure 21: Measured SNDR dependency for varying input frequency for a 2.35 Vpp input tone." width="500" >}}
Table 1: Comparison of State-of-The-Art ADC specifications
| **Parameter** | Unit | [^18] | [^23] | [^7] | [^13] | [^38] | [^39] | [^40] | [^41] | [^6] | **This Work** |
|----|----|----|----|----|----|----|----|----|----|----|----|
| **Year** | | 2007 | 2014 | 2015 | 2015 | 2016 | 2016 | 2016 | 2016 | 2017 | **2017** |
| **Tech.** | [nm]| 180 | 65 | 180 | 65 | 110 | 65 | 180 | 55 | 180 | **180** |
| **Topology** | | SAR | NSSAR | IADC | NSSAR | SAR | SAR | IADC | NSSAR | IADC | \textbf{(\Delta\Sigma)SAR} |
| **Supply-V** | [V] | 1 | 0.8 | 1.8 | 0.8 | 0.9 | 0.4 | 1.8 | 1.2 | 1.5 | **1.2** |
| **Supply-I** | [\mmu A] | 25 | 1.7 | 19 | 151 | 27 | 1.8 | 16.4 | 13.1 | 23 | **4.3** |
| **Speed** | [S/s] | 100 k | 32 k | 8 k | 6.25 M | 1 M | 1 k | 313 k | 4 k | 2 k | **200 k ** |
| **ENOB** | [bits] | 10.55 | 12.4 | 12.3 | 9.35 | 11.0} | 7.81 | 9.3 | 15.7 | 16.1 | **10.8**} |
| **SNDR** | [dB] | 65 | 76 | 75 | 58 | 67 | 49 | 57 | 96 | 97 | **67**} |
| **Area** | [mm²] | 0.63 | 0.18 | 0.33 | 0.012 | 0.097 | 0.013 | 0.002 | 0.072 | 0.5 | **0.016 ** |
| **FOMW** | [fJ/conv] | 165 | 8 | 862 | 14.8 | 11.7 | 3.19 | 151 | 73.8 | 320 | **14**} |
| **FOMS** | [dB] | 156 | 177 | 159 | 163 | 170 | 137 | 154 | 180 | 175 | **170**} |
In Table 1 the performance is summarized and state-of-the-art noise shaping ADC structures are compared. This work achieves exceptional compactness for the 12 bit target resolution particularly in relation to the conversion efficiency [^37]}. The measured power dissipation is about 5 \mmu W of which simulations indicate 40% is dissipated in the loop filter and 23% in capacitive switching. Note that power dissipation from the look up table is not included in this figure. Fig. 20 presents the measured SNDR and \\(FOM_{W}\\) for varying oversampling ratios. During calibration the OSR was doubled to gain 3 dB in precision while the typical operation uses an \\(OSR\\) of 24.} The total conversion uses an additional 11 cycles for SAR and sampling phases to give the resulting 200 kS/s speed for a 7 MHz system clock. We also show the measured SNDR for varying input frequencies in Fig. 21. This shows that maximum precision is maintained for signals below 20 kHz but also shows some degradation at frequencies near the maximum input bandwidth. The main experimental difficulty resulting from the proposed configuration is that the filter characteristics are closely tied to the reference voltage in a practical setting. On occasion it is useful to give additional voltage overhead for aggressive digital and analogue systems to accommodate process voltage and temperature variance. However in this case the biasing circuit will need extra tuning parameters to keep the modulator's linearity consistent while adjusting the reference voltage. Multi channel systems can generally accommodate complex tuning for all ADCs to eliminate wafer/process level variations without substantial overhead since this functionality is already needed by instrumentation circuits to perform precise filtering. The power management block in Fig. 13 provides 12 bit digital trimming on the ADC reference voltages and bias currents such that most of the off-set can be accommodated although this is performed externally on the test structure.}
# 14 Conclusion
A novel 12-bit analogue-to-digital data converter has been proposed that uses SAR & \\(\Sigma\Delta\\) quantization schemes to realize a compact and ultra low power data converter for a 64 channel neural sensor system. Using an efficient Gm-C filter, compact 7 bit binary DAC, and optimized FIR decimation this work aims to eliminate the circuit complexity from DEM and increase power efficiency which is highly desirable for biomedical sensors.} A prototype fabricated in \cmostech demonstrates 10.8 ENOB precision at the nyquist frequency with a state-of-the-art 0.016 mm² silicon footprint and is capable of resolving full scale signals at 200 kS/s.} The proposed techniques are appropriate for a variety of sampling frequencies making this configuration applicable to numerous other applications that require aggressive ADC miniaturization. In addition a calibration technique suitable for large sensor arrays is presented that takes advantage of the two step quantization scheme to calibrate multiple ADCs simultaneously.}
# 15 Acknowledgement
The authors would like to thank Nicolas Moser and the reviewers for helpful comments and assistance with improving this manuscript.
# Refernces:
[^35]: B.E. Boser and B.A. Wooley, ''The design of sigma delta modulation analog to digital converters,'' IEEE Journal of Solid-State Circuits, vol.23, no.6, pp. 1298--1308, Dec 1988.
[^4]: A.Agah etal., ''A high-resolution low-power incremental $\Sigma \Delta$ ADC with extended range for biosensor arrays,'' IEEE Journal of Solid-State Circuits, vol.45, no.6, pp. 1099--1110, June 2010.
[^30]: P.Nuzzo etal., ''Noise analysis of regenerative comparators for reconfigurable ADC architectures,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.55, no.6, pp. 1441--1454, July 2008.
[^8]: Y.Chae, K.Souri, and K.A.A. Makinwa, ''A 6.3$ \mu$W 20$ $bit incremental zoom-adc with 6 ppm INL and 1 $\mu$V offset,'' IEEE Journal of Solid-State Circuits, vol.48, no.12, pp. 3019--3027, Dec 2013.
[^24]: J.Huang, S.Yang, and J.Yuan, ''A 75 dB SNDR 10-MHz signal bandwidth gm-c-based sigma-delta modulator with a nonlinear feedback compensation technique,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.62, no.9, pp. 2216--2226, Sept 2015.
[^34]: R.Webster, ''A generalized hamming window,'' IEEE Transactions on Acoustics, Speech, and Signal Processing, vol.26, no.3, pp. 269--270, Jun 1978.
[^1]: K.Famm etal., ''Drug discovery: a jump-start for electroceuticals,'' Nature, vol. 496, no. 7444, pp. 159--161, April 2013.
[^15]: L.B. Leene and T.G. Constandinou, ''A 2.7$ \mu$W/MIPS, 0.88$ $GOPS/mm$^2$ distributed processor for implantable brain machine interfaces,'' in IEEE Proceedings of the Biomedical Circuits and Systems Conference, October 2016, pp. 360--363.
[^14]: L.B. Leene, Y.Liu, and T.G. Constandinou, ''A compact recording array for neural interfaces,'' in IEEE Proceedings of the Biomedical Circuits and Systems Conference, October 2013, pp. 97--100.
[^31]: X.Yue, ''Determining the reliable minimum unit capacitance for the DAC capacitor array of SAR ADCs,'' Microelectronics Journal, vol.44, no.6, pp. 473 -- 478, 2013.
[^23]: P.Harpe, E.Cantatore, and A.van Roermund, ''An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1 dB SNDR,'' in IEEE Proceedings of the International Solid-State Circuits Conference, February 2014, pp. 194--195.
[^41]: Y.S. Shu, L.T. Kuo, and T.Y. Lo, ''An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55 nm CMOS,'' IEEE Journal of Solid-State Circuits, vol.51, no.12, pp. 2928--2940, Dec 2016.
[^36]: B.D. Vuyst etal., ''The nyquist criterion: A useful tool for the robust design of continuous-time $\Sigma \Delta$ modulators,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.57, no.6, pp. 416--420, June 2010.
[^19]: V.Balasubramanian etal., ''A 0.18$\mu$m biosensor front-end based on 1/f noise, distortion cancelation and chopper stabilization techniques,'' IEEE Transactions on Biomedical Circuits and Systems, vol.7, no.5, pp. 660--673, Oct 2013.
[^21]: Y.Tao and Y.Lian, ''A 0.8-V, 1-mS/s, 10-bit SAR ADC for multi-channel neural recording,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.62, no.2, pp. 366--375, Feb 2015.
[^20]: Z.Zhu and Y.Liang, ''A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-$\mu$m CMOS for medical implant devices,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.62, no.9, pp. 2167--2176, Sept 2015.
[^2]: K.Abdelhalim etal., ''64-channel UWB wireless neural vector analyzer SoC with a closed-loop phase synchrony-triggered neurostimulator,'' IEEE Journal of Solid-State Circuits, vol.48, no.10, pp. 2494--2510, Oct 2013.
[^17]: J.C. Candy and G.C. Temes, The Design of Sigma Delta Modulation Analog to Digital Converters.\hskip 1em plus 0.5em minus 0.4em
elax Wiley-IEEE Press, 1992, pp. 293--303.
[^26]: W.Liu, P.Huang, and Y.Chiu, ''A 12-bit, 45-mS/s, 3-mW redundant successive-approximation-register analog-to-digital converter with digital calibration,'' IEEE Journal of Solid-State Circuits, vol.46, no.11, pp. 2661--2672, Nov 2011.
[^27]: H.S. Lee, D.A. Hodges, and P.R. Gray, ''A self-calibrating 15 bit CMOS A/D converter,'' IEEE Journal of Solid-State Circuits, vol.19, no.6, pp. 813--819, Dec 1984.
[^7]: S.Tao and A.Rusu, ''A power-efficient continuous-time incremental sigma-delta ADC for neural recording systems,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.62, no.6, pp. 1489--1498, June 2015.
[^16]: R.Schreier, ''An empirical study of high-order single-bit delta-sigma modulators,'' IEEE Transactions on Circuits and Systems---Part II: Analog and Digital Signal Processing, vol.40, no.8, pp. 461--466, Aug 1993.
[^13]: Z.Chen, M.Miyahara, and A.Matsuzawa, ''A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC,'' in IEEE Proceedings of the Symposium on VLSI Circuits, June 2015, pp. C64--C65.
[^12]: Z.Chen, M.Miyahara, and A.Matsuzawa, ''A stability-improved single-opamp third-order $\Delta\Sigma$ modulator by using a fully-passive noise-shaping SAR ADC and passive adder,'' in IEEE Proceedings of the European Solid-State Circuits Conference, Sept 2016, pp. 249--252.
[^11]: Y.S. Shu, L.T. Kuo, and T.Y. Lo, ''An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55nm cmos,'' in IEEE Proceedings of the International Solid-State Circuits Conference, January 2016, pp. 458--459.
[^3]: J.M. dela Rosa etal., ''Next-generation delta-sigma converters: Trends and perspectives,'' IEEE Transactions on Emerging and Selected Topics in Circuits and Systems, vol.5, no.4, pp. 484--499, Dec 2015.
[^40]: I.Lee, B.Kim, and B.G. Lee, ''A low-power incremental delta-sigma ADC for CMOS image sensors,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.63, no.4, pp. 371--375, April 2016.
[^6]: Y.Zhang etal., ''A 16 b multi-step incremental analog-to-digital converter with single-opamp multi-slope extended counting,'' IEEE Journal of Solid-State Circuits, vol.52, no.4, pp. 1066--1076, April 2017.
[^33]: E.Nunzi, P.Carbone, and D.Petri, ''Estimation of the in-band delta--sigmanoise power based on windowed data,'' IEEE Transactions on Instrumentation and Measurement, vol.55, no.6, pp. 2221--2226, Dec 2006.
[^39]: P.Harikumar, J.J. Wikner, and A.Alvandpour, ''A 0.4-V subnanowatt 8-bit 1-kS/s SAR ADC in 65-nm cmos for wireless sensor applications,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.63, no.8, pp. 743--747, Aug 2016.
[^5]: C.H. Chen etal., ''A micro-power two-step incremental analog-to-digital converter,'' IEEE Journal of Solid-State Circuits, vol.50, no.8, pp. 1796--1808, Aug 2015.
[^10]: J.A. Fredenburg and M.P. Flynn, ''A 90-mS/s 11-MHz-bandwidth 62-dB SNDR noise-shaping SAR ADC,'' IEEE Journal of Solid-State Circuits, vol.47, no.12, pp. 2898--2904, Dec 2012.
[^25]: D.J. Chang etal., ''Normalized-full-scale-referencing digital-domain linearity calibration for SAR ADC,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.64, no.2, pp. 322--332, Feb 2017.
[^29]: K.Lee, M.R. Miller, and G.C. Temes, ''An 8.1 mW, 82 dB delta-sigma ADC with 1.9 MHz BW and -98 dB THD,'' IEEE Journal of Solid-State Circuits, vol.44, no.8, pp. 2202--2211, Aug 2009.
[^28]: J.Silva etal., ''Wideband low-distortion delta-sigma ADC topology,'' Electronics Letters, vol.37, no.12, pp. 737--738, Jun 2001.
[^22]: F.Gerfers, M.Ortmanns, and Y.Manoli, ''A 1.5-V 12-bit power-efficient continuous-time third-order sigma; delta; modulator,'' IEEE Journal of Solid-State Circuits, vol.38, no.8, pp. 1343--1352, Aug 2003.
[^9]: A.Sanyal, L.Chen, and N.Sun, ''Dynamic element matching with signal-independent element transition rates for multibit $\Delta\Sigma$ modulators,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.62, no.5, pp. 1325--1334, May 2015.
[^32]: E.Hogenauer, ''An economical class of digital filters for decimation and interpolation,'' IEEE Transactions on Acoustics, Speech, and Signal Processing, vol.29, no.2, pp. 155--162, Apr 1981.
[^38]: Y.H. Chung, C.W. Yen, and M.H. Wu, ''A 24-$\mu$W 12-bit 1-mS/s SAR ADC with two-step decision DAC switching in 110-nm cmos,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.24, no.11, pp. 3334--3344, Nov 2016.
[^18]: N.Verma and A.P. Chandrakasan, ''An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes,'' IEEE Journal of Solid-State Circuits, vol.42, no.6, pp. 1196--1205, June 2007.

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---
title: "A 0.5 V time-domain instrumentation circuit with clocked and unclocked ΔΣ operation"
date: 2017-05-28T15:26:46+01:00
draft: false
toc: true
math: true
type: posts
tags:
- publication
- instrumentation
- CMOS
- time-domain
- circuit
---
Lieuwe B. Leene, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
This paper presents a time-domain instrumentation circuit with exceptional noise efficiency directed at using nano metre CMOS for next generation neural interfaces. Current efforts to realize closed loop neuromodulation and high fidelity BMI prosthetics rely extensively on digital processing which is not well integrated with conventional analogue instrumentation. The proposed time-domain topology employs a differential ring oscillator that is put into feedback using a chopper stabilized low noise transconductor and capacitive feedback. This realization promises better digital integration by extensively using time encoded digital signals and seamlessly allows both clocked & unclocked \\(\Delta\Sigma\\) behavior which is useful on-chip characterization and interfacing with synchronous systems. A 0.5 V instrumentation system is implemented using a 65 nm TSMC technology to realize a highly compact footprint that is 0.006 mm² in size. Simulation results demonstrate an excess of 55 dB dynamic range with 3.5 \mmu V<sub>rms<sub> input referred noise for the given 810 nW total system power budget corresponding to an NEF of 1.64.
# 2 Introduction
Recent efforts to realize brain machine interfaces (BMI) target fully integrated neural recording systems that use advanced CMOS technologies to enable real time diagnostics for hundreds of channels simultaneously. This emerging trend is predominately motivated by the extensive use of digital techniques applied to robust therapeutic feedback for closed-loop neuromodulation and signal compression/feature extraction in high channel count BMIs for prosthetic motor control[^1]. However there are a growing number of challenges associated with integrating analogue instrumentation for these digital systems due to the loss in analogue transistor characteristics which has motivated the use of time domain (TD) analogue [^2]. TD systems encode information with respect to the timing intervals of asynchronous digital signals to perform mixed signal processing while extensively using standard logic and oscillators that do not suffer from analogue complications. Many recent publications will indicate the potential for exceptional dynamic range like in the recording system of [^3] or highly compact instrumentation like the potentiostat in \cite{VCO_SENSE2}. We argue that a key advantage for these systems is that supply voltage is utilized more effectively from a fundamental aspect without being impeded by linearity. This allows an aggressive reduction in power dissipation. Furthermore realizing band limiting filters outside the instrumentation loop prevents KT/C relations from limiting the compactness of the system.
{{< figure src="/images/iscas2017/TDI.svg" title="Figure 1: TD system architecture for BMI systems where both the instrumentation and processing sub-blocks manipulate time-encoded signals to perform feature extraction from bio-signal recordings. This paper will present the instrumentation sub-system." width="500" >}}
This work presents a TD instrumentation topology for neural recording applications that targets ultra-low power operation and a highly compact implementation for miniaturized multichannel systems. Based on previous work in [^4], which uses a third order feedback loop to digitize the signal asynchronously, this realization exhibits only one dominant pole and thus reduces the resources spent on achieving stability. While [^4] can achieve a smaller footprint than the topology presented here the feed-forward structure cannot achieve high dynamic range as the high frequency quantization noise and out of band distortion from the counter cannot be suppressed without additional filtering. Our current efforts aim to realize the system architecture illustrated in Fig. 1. This approach aims to use the efficiency of TD processing techniques to extract features from neural recordings which promise an order of magnitude improvement over conventional implementations [^5]. In fact such a TD approach has already been applied to acquire wireless radio signals with a versatile activity dependent power dissipation [^6]. However there will be numerous scenarios where these asynchronous structures must interface with clocked systems to effectively perform calibration or other discrete time analysis. For this reason we specifically consider how the class of circuits presented here and in [^5] can seamlessly realize a more traditional clocked \\(\Delta\Sigma\\) oversampling loops. This is relevant because time encoded signals have a very broad bandwidth of several GHz making it unreasonable to characterize or communicate a large number of them off chip. Finding effective means to convert such time-encoded signals to a clocked and quantized equivalent is crucial for fully integrated systems. This paper is organized as follows; First the basic structure of the proposed circuit is introduced in Sec. \ref{Sec:architecture} which motivates the general topology chosen here. Then in Sec. \ref{Sec:circuit} we shall detail the circuit level implementation and identify important design considerations. Finally Sec. \ref{Sec:simulation} presents the preliminary simulation results which leads to the conclusions in Sec. \ref{Sec:conclusion}.
# 3 Time-Domain Instrumentation Architecture
The proposed configuration is shown in Fig. 2 as a single ended equivalent of the fully differential system implemented here. The neural signals picked up on V<sub>IN<sub> include local field potentials of several millivolt and extracellular action potential from nearby neural tissue with 100 microvolt amplitudes where the total bandwidth of interest here is from near DC to 6 kHz[^1]. Using a reference electrode these components are first chopped to a higher frequency f<sub>chp<sub> at 100 kHz. This is then passed into a capacitive network that allows the digital output signal Q to be directly feedback onto the input after using a XOR gate realize chopper modulation. The intermediate node V<sub>G<sub> is tapped off to a transconductive cell which advances/recedes the phase of a multi stage ring oscillator structure after the signal is chopped back to the base band. By referencing the phase of this oscillator to another oscillator we can realize the time-encoded digital signal that encodes the phase difference \pphi<sub>\dDelta<sub> as pulse width modulated information. Then we may either quantize this signal with a register in the time domain or simply buffer it onto Q to provide asynchronous feedback without time quantization. Now the near-DC aggressors such as off-set and flicker noise from the transconductor are neutralized using the feedback loop through R<sub>p<sub> which presents a high pass response for signals below the chopper frequency on node V<sub>G<sub>. If we simply take the transconductor, oscillator, and digital logic to represent some kind of integrator then the high level instrumentation topology reduces to a relatively simple chopper stabilized circuit. Finally in the synchronous case where time is quantized, the output Q is passed into a second order cascaded integrator–comb (CIC) filter that decimates oversampled signals into discrete samples. Otherwise \pphi<sub>\dDelta<sub> is simply passed onto other TD processing structures which is outside the scope of this paper.
{{< figure src="/images/iscas2017/TDA.svg" title="Figure 2: The proposed chopper stabilized instrumentation system that uses a ring oscillator to realize TD based first order integration with respect to the output phase difference which is then quantized in time and decimated using a CIC filter. " width="500" >}}
We highlight the fact that the high pass feedback uses the output referred signal. This has a profound effect on how the noise profile of R<sub>p<sub> appears at the chopper frequency when referred to the input. In fact if R<sub>p<sub> was tied to a biasing voltage to set V<sub>G<sub> then resistor's noise will have a rms power of \\(√{kT/C_{IN}}\\) at the input that is up modulated and will corrupt the linearity of the integrator. This can be very substantial because C<sub>IN<sub> is reduced to 100 fF in order to boost the input impedance that depends on the chopping frequency as R<sub>IN<sub>=1/(f<sub>chp<sub>C<sub>IN<sub>). This feedback configuration reduces this noise component as a function of closed loop gain A<sub>cl<sub> which is maximized as we realize all the necessary signal gain in a single analogue processing stage. Moreover the chopper stabilization allows an aggressive reduction on input transistor size which is important for reducing parasitics on the node V<sub>G<sub>. Any parasitic loading here can prevent further reduction in C<sub>IN<sub> because it would degrade the noise performance.
The PWM signals \pphi<sub>\dDelta<sub>, Q, and X in Fig. 2 are illustrated in bold because they represent multiphase time-encoded signals by simultaneously taping off multiple phases inside the oscillator and using them in parallel. The capacitive feedback network sums these signals to acquire an analogue equivalent where the number of amplitude quantization levels is 1+N for N phases used in parallel. This is an important point because the error signal on V<sub>G<sub> is a function of the supply voltage as V<sub>DD<sub>/(N A<sub>cl<sub>) which must lie well within the linear range of the transconductor. Adding to the fact that supply noise is also inversely proportional to A<sub>cl<sub> reveals that although we can reduce power by reducing V<sub>DD<sub>, this parameter is tightly coupled to other performance requirements. In fact using the definition of noise efficiency factor NEF from [^7] one can derive the following expression to predict the system power P<sub>sys<sub> for noise limited systems:
$$ P_{sys} = V_{DD} \omega_{3dB} \frac{kT U_T}{e^2_{in}} NEF^2 $$
Eq. 1 uses \\(\omega\\)<sub>3dB<sub>, kT, U<sub>T<sub>, and e²<sub>in<sub> as the signal bandwidth in radians, Boltzmann energy, thermal voltage, and input referred noise power. This expression ignores any constraints due to sampling noise or capacitor sizing that could suffer as the supply voltage decreases. However it clearly illustrates our motivation for reducing power through V<sub>DD<sub> which is allowed in this fashion only if no band limiting behavior is required from the instrumentation loop. In fact an important contribution here is that a near ideal NEF is achieved for the TD structure using the proposed implementation.
# 4 Circuit Implementation
{{< figure src="/images/iscas2017/TDS.svg" title="Figure 3: Transistor level implementation of a) the low noise amplifier and b) high pass filter circuit that removes flicker noise and off-set. A legend is presented in gray showing how a) & b) relate to Fig. 2 and the chopper in a) is omitted for clarity." width="500" >}}
The fully differential analogue part of this system is shown in Fig. 3. Here two analogue structures are shown, one for signal amplification that integrates on the differential phase \pphi<sub>\dDelta<sub> which we shall consider the amplifier. The second structure presents the pseudo resistor that rejects the low frequency aggressors that are being up modulated onto the output Q which we will refer to as the high pass filter. The amplifier is composed of a complementary transcondutor to boost the noise efficiency and is loaded by two ring oscillators that are biased with a current I<sub>X<sub> that is 16x smaller than I<sub>B<sub> such that the input referred noise from the oscillator to V<sub>G<sub> is greatly reduced. A XOR gate is used to compute the phase difference of the two oscillators because it does not have a discontinuity in its phase to PWM characteristic. The floating ground of both oscillators is tied together to reject common mode noise and minimize any coupling to the analogue power supplies.
Actually, the high pass filter not only performs feedback but also determines the common mode input voltage on V<sub>G<sub>. This mechanism is used to set the common mode on V<sub>X<sub> to V<sub>CM<sub> using the transistors M5-M8. This is important because the oscillator needs to run in the middle of the rail to allow more efficient conversion from the small internal voltage oscillation of 300 mV to a digital signal with full swing. The reason a current DAC is used to drive the pseudo resistors is because the linearity of these devices is important and R<sub>p<sub> can only handle \\(\pm\\)100 mV if simple diode connected devices are used. This is why C<sub>L<sub> is introduced to provide some filtering and minimize distortion from the high frequency PWM feedback. Note that because all transistors will use subthreshold operation the threshold voltage V<sub>TH<sub> difference between the input PMOS pair M3-M4 and the high V<sub>TH<sub> devices M9-M10 will represent voltage headroom of the PMOS current bias which should at least be 100 mV.
Now there is quite a significant impact from using an oscillator as load for the amplifier structure in this particular fashion. It may be obvious that there are no high impedance analogue nodes in this configuration that could introduce undesirable poles. But more importantly we do not need to provide extra voltage headroom or a second gain stage to let our output signal vary with maximum amplitude. This proposed implementation allows both simplicity and high power efficiency. In this case the oscillator mostly reuses the V<sub>TH<sub> voltage headroom needed by the NMOS input transistors. This raises an interesting question; what limits the required voltage headroom for this circuit? Typically the complementary structure necessitates that the source drain voltage of the current bias transistors and differential pairs is sufficient to provide good channel resistance. However there is another component with regard to the noise generated by the oscillator that should be considered in terms of the oscillator voltage overhead V<sub>RO<sub>. Consider the noisy charge induced as sampling noise from one of the oscillators on each inverter gate capacitance C<sub>gate<sub> before the up/down transition as residue from the previous cycle. This can be represented by an equivalent noisy current source **i**²<sub>smp<sub> using the oscillator frequency f<sub>osc<sub> as formulated in Eq 2.
$$ i^2_{smp} = 2N f^2_{osc} kT C_{gate} $$
Referring this component to V<sub>G<sub> as input referred voltage noise equivalent **v**²<sub>smp<sub> requires f<sub>osc<sub> to be represented in terms of total charge dissipated each cycle f<sub>osc<sub>=I<sub>X<sub>/(2N V<sub>RO<sub> C<sub>gate<sub>). Taking the transconductance of the amplifier approximately as Gm\\(\approx\\)2I<sub>B<sub>/(\\(\eta\\) U<sub>T<sub>) will resolve the expression as in Eq 3 using \\(\eta\\) and U<sub>T<sub> as slope factor and thermal voltage.
$$ v^2_{smp} = \frac{i^2_{smp}}{Gm^2} = \frac{2 kT}{P_{osc}} \left( \eta U_T \frac{I_X}{2 I_B} \right)^2 $$
This result may be surprising in some sense because indicates the oscillator should dissipate a strict amount of energy to avoid this noise component from being significant. The only way to do this is by increasing the V<sub>RO<sub> because increasing its bias current I<sub>X<sub> will in fact degrade the input referred noise. Also notice that the actual capacitive load of the oscillator does not impact the thermal noise floor although it is directly related to the bandwidth of operation. In this particular case we configured the oscillation frequency to be around 300 kHz after optimization which implies that the effective frequency is around 1.5 MHz given the 5 phases. For this reason when the CIC filter is enabled we use a 3 MHz system clock for time quantization and an over sampling ratio of 128. This implies that the instrumentation bandwidth will be limited to 11 kHz sampled at exactly 22 kS/s.
# 5 Simulation Results
The presented implementation was fabricated using the commercially available TSMC 65 nm CMOS LP MS RF technology (1P9M 6X1Z1U RDL). This system can operate at 0.5 V by extensively using the different V<sub>TH<sub> process options for the standard transistor. Fig. 4 shows the floor plan and final fabricated device and the MIM capacitors covering the active area. A compact configuration was achieved with a 0.006mm² footprint where future work could potentially share the biasing and digital filter resources. Our preliminary results consist of post layout noise simulations that should have a good degree of precision for predicting the expected bench top measurements. Fig 5 shows the ring oscillator output with 200 mV amplitude in the middle of the rail that is fed to the XOR gate to produce the full swing digital signal \pphi<sub>\dDelta<sub>. Fig 6 shows the output of the circuit in the frequency domain before & after decimation by the CIC filter. We can observe that linearity is quite easily achieved due to the exceptional loop gain from the TD integrator and because all analogue nodes exhibit a small signal swing. The performance summary in Table 1 compares this work to recently published instrumentation systems using the 65nm or 90nm technology node. Notice that a comparable noise performance is achieved for a similar if not better input dynamic range while the NEF & area characteristics are respectable given the extra capability that signal quantization is also performed. The input resistance due to chopping for this configuration is estimated to be 57 M\\(\Omega\\) which will be sufficient for most integrated neural recording electrodes.
{{< figure src="/images/iscas2017/LAY.svg" title="Figure 4: The floor plan and micro photograph of the fabricated TD instrumentation prototype. " width="500" >}}
{{< figure src="/images/iscas2017/DIG2.svg" title="Figure 5: Simulation results showing a) the two ring oscillator outputs & b) the respective phase difference signal due to a 5 mVpp sinusoidal signal at 2 kHz at the input of the instrumentation system." width="500" >}}
{{< figure src="/images/iscas2017/SPC2.svg" width="500" >}}
{{< figure src="/images/iscas2017/SPC.svg" title="Figure 6: Spectral characteristics of a) the \\(\Delta\Sigma\\) modulator and b) the CIC filter output due to a 2 kHz 5 mVpp sinusoidal input showing a precision of 54.8 dB SINAD and no visible harmonics due to distortion." width="500" >}}
Table 1: Performance summary and comparison with state of the art.
| Specification | This Work | [^8] | [^9] | [^10] |
|----|----|----|----|----|
| Modality | Time | Volt. | Volt. | Volt. |
| Technology | 65nm | 90nm | 65nm | 65nm |
| Supply [V] | 0.5 | 1 | 1 | 1 |
| Supply [A] | 2.65\mmu (\dagger) | 2.85\mmu | 1**n** | 3.28\mmu |
| Gain [dB] | 46 | 59 | 32 | 52 |
| Bandwidth [Hz] | 11 **k** | 10.5 **k** | 370 | 8.2 **k** |
| SINAD [dB] | 53 | (>)40 | 57 | (>)40 |
| IRN [V<sub>rms<sub>] | 3.8\mmu | 3.04\mmu | 26\mmu | 4.13\mmu |
| NEF | 2.2 | 1.93 | 2.1 | 3.19 |
| Area [mm²] | 0.006(\star) | 0.137 | 0.168(\star) | 0.042 |
\\(^\star\\) Includes ADC area. \\(^\dagger\\) Includes axillary and biasing circuits.
# 6 Conclusion
This work realizes a chopper stabilized \\(\Sigma\Delta\\) modulator right at the sensor interface using a time-domain topology for ultra low voltage operation. The proposed oscillator based instrumentation circuit addresses a number of the challenges associated with instrumentation using nano metre CMOS technologies. This system has a power budget of 810 nW and a compact silicon foot print of 0.006 mm². Moreover this system can achieve a NEF of 1.64 while including the power dissipation due to quantizing the signal with 8.8 effective number of bits at 22 kS/s.
# 7 Acknowledgment
This work was supported by EPSRC grants EP/K015060/1 and EP/M020975/1.
# Refernces:
[^1]: H.Kassiri etal., ''Battery-less tri-band-radio neuro-monitor and responsive neurostimulator for diagnostics and treatment of neurological disorders,'' IEEE J. Solid-State Circuits, vol.51, no.5, pp. 1274--1289, May 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2528999
[^3]: W.Jiang etal., ''A ±50mv linear-input-range vco-based neural-recording front-end with digital nonlinearity correction,'' in IEEE Proc. ISSCC, January 2016, pp. 484--485. [Online]: http://dx.doi.org/10.1109/ISSCC.2016.7418118
[^2]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-mode operational amplifiers and their application to continuous-time filters in nanoscale cmos,'' IEEE J. Solid-State Circuits, vol.49, no.12, pp. 2758--2772, December 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2354641
[^6]: M.Kurchuk etal., ''Event-driven ghz-range continuous-time digital signal processor with activity-dependent power dissipation,'' IEEE J. Solid-State Circuits, vol.47, no.9, pp. 2164--2173, September 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2203459
[^10]: K.A. Ng and Y.P. Xu, ''A low-power, high cmrr neural amplifier system employing cmos inverter-based otas with cmfb through supply rails,'' IEEE J. Solid-State Circuits, vol.51, no.3, pp. 724--737, March 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2512935
[^9]: P.Harpe etal., ''A 0.20$ $mm$^2$ 3$ $nw signal acquisition ic for miniature sensor nodes in 65 nm cmos,'' IEEE J. Solid-State Circuits, vol.51, no.1, pp. 240--248, Jan 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2487270
[^8]: T.Yang and J.Holleman, ''An ultralow-power low-noise cmos biopotential amplifier for neural recording,'' IEEE Trans. Circuits Syst. II, vol.62, no.10, pp. 927--931, Oct 2015. [Online]: http://dx.doi.org/10.1109/TCSII.2015.2457811
[^7]: M.S.J. Steyaert and W.M.C. Sansen, ''A micropower low-noise monolithic instrumentation amplifier for medical purposes,'' IEEE J. Solid-State Circuits, vol.22, no.6, pp. 1163--1168, December 1987. [Online]: http://dx.doi.org/10.1109/JSSC.1987.1052869
[^4]: M.Elia, L.B. Leene, and T.G. Constandinou, ''Continuous-time micropower interface for neural recording applications,'' in IEEE Proc. ISCAS, May 2016.
[^5]: L.B. Leene and T.G. Constandinou, ''A 0.45v continuous time-domain filter using asynchronous oscillator structures,'' in IEEE Proc. ICECS, December 2016, pp. 49--52. [Online]: http://dx.doi.org/10.1109/ICECS.2016.7841129

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Lieuwe B. Leene, Timothy G. Constandinou
Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
# 1 Abstract
The ability to process time-encoded signals with high fidelity is becoming increasingly important for time domain (TD) circuit techniques that are used at advanced nanometre technology nodes. This work proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation (PWM) encoded signals and makes extensive use of digital logic, enabling low voltage operation. First and second order primitives are introduced that can be used as TD memory or to enable analogue filtering of TD signals. These structures can be modelled precisely to realise more advanced linear or nonlinear functionality using an ensemble of units. This paper presents the measured results of a prototype fabricated using a 65 nm CMOS technology to realise a 4\\(^{th}\\) order lowpass Butterworth filter. The system utilises a 0.5 V supply voltage with asynchronous digital control for closed-loop operation to achieve a 73 nW power budget. The implemented filter achieves a maximum signal to noise and distortion ratio (SNDR) of 53 dB with a narrow 5 kHz bandwidth resulting in an figure-of-merit (FOM) of 8.2 fJ/pole. With this circuit occupying a compact 0.004 mm² silicon footprint, this technique promises a substantial reduction in size over conventional Gm-C filters whilst additionally offering direct integration with digital systems.
# 2 Introduction
Modern digital architectures and energy constrained devices are being increasingly challenged by device variability and probabilistic computation that are incompatible with today's digital paradigm [^1]. In contrast, many biological processes such as the human visual system are robust to such challenges. This has inspired research to explore alternative means for signal representation and computation based on phenomena observed in the natural world [^2]. This has led to the re-emergence of processing in the analogue domain as an 'accelerator' inside a digital framework[^3]. This is because the efficiency of analogue processing can be far superior to its digital equivalent for specific applications[^4][^5]. However there remain many challenges that in practice prevent such architectures from achieving a clear advantage. Current systems demand an integrated System on Chip (SoC) solution using digital CMOS technologies to realise cost effective performance. This substantially degrades analogue performance and ultimately leads to the use of time domain (TD) circuits to mitigate a number of these issues[^6]. Out of the different signal modalities that have been established: continuous-time continuous value (i.e. traditional analogue), discrete-time continuous value (i.e. switched cap analogue), discrete-time discrete value (i.e. traditional digital), these TD circuits represent the continuous-time discrete value (i.e. asynchronous digital) approach of representing information.
TD systems rely on encoding signals in terms of the delay between instantaneous events such as clock edges or digital pulses that can be manipulated using asynchronous or synchronous digital logic with very high efficiency[^7]. The nature of digital provides immunity to supply noise and flexibility in signal representation that is less sensitive to operating conditions when compared to conventional voltage or current mode processing. In fact these techniques are becoming increasingly more widespread in recent years extending from the typical use in phase locked loops (PLL) towards sensing[^8] and processing applications[^9]. Moreover the ongoing trends in supply voltage reduction and technology scaling will lead to the time-based alternatives becoming increasingly more favourable for digital system integration[^10].
{{< figure src="/images/tcas2016/td_system.svg" title="Figure 1: Concept of processing multi-phase time-encoded signals using digital logic, in combination with oscillator-based memory elements for retaining system states." width="500" >}}
It is becoming increasingly important to establish which techniques can process time-encoded signals in a way that is robust towards noisy digital environments and the nonlinear characteristics of nanometre-scale CMOS. Several methods have already been developed for PLL subsystems such as using noise to linearise time quantisation[^11] or using two-dimensional vernier lines to perform noise shaping[^12]. One example of a TD processing system is the event-driven digital filter [^13] that uses a reconfigurable delay line to process TD signals asynchronously. This work applies different weights to the delay line outputs to realise finite impulse response (FIR) filtering without introducing clocked time quantization.
Delay based techniques for amplification[^14], addition[^15], and subtraction[^15] have been particularly successful for MHz/GHz signals but tend to be incompatible with low frequency control or when dealing with signals of dissimilar bandwidths. This drawback is also characteristic of FIR techniques due to the fact that millisecond delay lines are easily prone to noisy aggressors and may require an exhaustive number of delay elements. Other systems use open loop voltage-controlled oscillator (VCO) structures for transducing low frequency signals with reduced complexity[^16][^17]. These tend to rely on the linearity of capacitive discharge or voltage-controlled frequency generation for precise processing. However this dependency is particularly vulnerable to process, voltage and temperature variations or device dependent nonlinearities if correction/compensation is not performed. Digital techniques have been proposed to reduce the overhead from correction logic[^8] but it would be desirable to reduce such sensitivities.
This work proposes a ring oscillator based filter (ROF) structure that reduces the complexity of existing TD systems to realise a compact TD filter with closed loop operation for ultra-low-power computationally intensive applications[^18][^19]. The dynamics of this architecture are, in some way, similar to asynchronous delta sigma modulators[^20] or asynchronous delta modulators[^21][^22]. The difference is that the input and output are time-encoded signals such that the functionality is strictly focused on processing. This is illustrated in Fig. 1. This topology aims to exclusively use digital logic and asynchronous control loops to adjust the phase of an oscillator which is in turn used to generate digital feedback signals to realise a continuous-time dynamical system or infinite impulse response (IIR) in the digital domain.
Similarly to the three prior works, the presented implementation also targets near-threshold voltage operation by reducing or in this case eliminating the analogue nodes that necessitate a large voltage swing. Instead the large signal components are encoded using an asynchronous digital representation. The presented technique rely on encoding phase using PWM signals and utilising current-controlled oscillators to achieve low distortion that do not require any overhead for calibration. This approach considers the oscillator as a TD memory element analogous to a capacitor in a Gm-C circuit. The resulting circuit is operated asynchronously but the concept of TD memory can also be found in clocked time to digital converters (TDC)[^23]. Furthermore, the auxiliary digital subsystem will feature additional functionality and flexibility in terms of event-driven/nonlinear outputs and gain control.
The remainder of this paper is organised as follows: Section 3 describes the basic first/second order ROF structures and 'analogue' processing characteristics; Section 6 elaborates on digital processing techniques for manipulating TD signals; Section 9 details the transistor level implementation; Section 14 presents measured results and device characteristics; and Section 20 concludes this work with respect to the achieved performance.
# 3 Analogue Processing using ROFs
The concept for the proposed topology that filters TD signals and allows local feedback without external clocking or control is shown in Fig. 1.
This uses digital control to switch a transconductive element adjusting the oscillator phase according to the intended filter response. The feedback utilises the anti-aliasing properties provided by the current controlled phase modulation to reject high frequency errors in the digital computation thereby allowing the approximate computation presented in Sec. 6.
{{< figure src="/images/tcas2016/TD_modes.svg" title="Figure 2: Analogy between conventional analogue circuits and TD circuits in relation to the four signal modalities." width="500" >}}
The different signal representations and associated processing domains are illustrated in Fig. 2. This shows how the oscillator-based processing concept presented herein relates to conventional analogue circuits, using phase information instead of magnitude to represent signals. Traditional analogue (continuous value and time) employs integration in voltage (or time) using a transconductive element that is loaded by a memory circuit. If the time however is discretized (i.e. sampled-time analogue), there is a requirement for a fast switch and large sampling capacitor. Alternatively, sampling the phase information of an oscillator can be achieved by simply using a clocked register (as the time encoded signal is inherently quantized). This implies that TD systems are able to utilize digital memories to significantly increase information capacity with minimal demand on resource. The analysis that follows develops expressions for this configuration by considering structures that are analogous to single and two-stage amplifiers[^24].
The oscillator's phase (φ) is extracted using an XOR-based phase detector (PD). By using a differential structure, the phase output will not need an external reference since the XOR output will represent the phase difference (\\(\Delta\\)φ) of two synchronized oscillators. In fact this phase measurement is a key feature that mitigates the need for external clocking or digital differentiation, as found in other realizations[^6][^10]. Moreover the XOR PD does not experience distortion from band-limiting digital gates such as the pulse swallowing seen in [^15]. Instead reducing the phase difference and equivalent PWM modulation depth leads to a smaller digital bandwidth requirement, which is not the case for the register based PD.
## 4 Single-Stage ROF
{{< figure src="/images/tcas2016/TD_L1.svg" title="Figure 3: Implementation of the single-stage ROF topology showing: (a) the switched current source driving an oscillator with closed loop feedback control of the TD signals D, Q, E; (b) the simplified s-domain equivalent model based on an ideal integrator in feedback." width="500" >}}
A block diagram of the single-stage ROF is shown in Fig. 3. The signals D & Q are PWM encoded TD signals that are compared and subsequently generate a third output that injects current into the differential oscillator such that the two pulse widths are matched. This control will either increase or decrease the relative phase and proportionally adjust the pulse width of Q in a closed loop fashion. The operation depends on the integral relationship that the output phase φ has with respect to injecting a small signal current i\tss{\\(\Delta\\)}. This is characterised using an impulse sensitivity function (ISF) originally developed for analysing CMOS oscillators [^25].
$$ \phi (t) = \int_{-\infty}^{t} \Gamma_{i\Delta}(\omega_0 , \tau) i_{\Delta}(\tau) \: d\tau $$
Eq. 1 models the ISF due to i\tss{\\(\Delta\\)} as \\(\Gamma_{i\Delta}\\). This implies the simplified s-domain model yields an integration factor k1\\(\approx\\)I\tss{\\(\Delta\\)}\\(\Gamma_{i\Delta}\\). Strictly the ISF is a cyclostationary function implying that \\(\Gamma\\) may have phase dependent sensitivity with respect to i\tss{\\(\Delta\\)}. However because the current is injected into the virtual supply node V<sub>R<sub>, this sensitivity is small as seen from \\(\Gamma_{ig}\\) in Fig. 10 and instead will be assumed phase independent (for clarity). This allows for a relatively simple argument to be made to estimate \\(\Gamma_{i\Delta}\\) for low-power ring oscillators because the low-voltage operation implies that essentially all biasing current will be used to charge and discharge capacitors on each oscillator node. More specifically the contribution of short circuit current is negligible due to strictly non-overlapping conduction of the NMOS & PMOS transistors in the oscillator and similarly the transistor area will be sufficiently small to assume that the gate leakage component is much smaller than I<sub>B<sub>.
Suppose q<sub>max<sub> is the amount of charge dissipated by the oscillator each period. Then it should follow that q<sub>max<sub> = I<sub>B<sub>/f<sub>osc<sub> by definition but this factor should also relate the total amount of capacitance switched every cycle as q<sub>max<sub> = N V<sub>RG<sub> C<sub>gate<sub>, where N, C<sub>gate<sub>, V<sub>RG<sub> are the number of oscillator stages, total capacitive load at the output of every oscillator stage, and voltage across the oscillator respectively. More interestingly if we now consider injecting some excess charge every cycle then its impact is simply normalised by q<sub>max<sub> leading to \\(\Gamma_{i\Delta}\\) = 2π/q<sub>max<sub>. The final result is that if this integrator is configured for unity-gain feedback its bandwidth can be summarised in Eq. 2.
$$ f_{3dB} = \frac{I_{\Delta}}{q_{max}} = f_{osc} \frac{I_{\Delta}}{I_{B}} = \frac{I_{\Delta}}{N V_{RG} C_{gate} } $$
These relations above are needed to point out a defining characteristic of the single-stage ROF which is that the oscillator frequency is directly related to the circuit bandwidth. Moreover in practice it would make sense that the ratio I\tss{\\(\Delta\\)}/I<sub>B<sub> is close to unity to maximise both bandwidth efficiency and minimise the input referred offset due to any difference in f<sub>osc<sub> between the two oscillators. A ratio larger than 1 inherently leads to nonlinearity as V<sub>RG<sub> will become strongly dependent on the dynamic current being switched and therefore vary f<sub>3dB<sub> as a function of input. Instead V<sub>RG<sub> should be well-defined in terms of the biasing current such that it can be estimated using sub-threshold device operation V<sub>RG<sub> = V<sub>th<sub>+η U<sub>T<sub> ln(2I<sub>B<sub>/I<sub>spec<sub>) where V<sub>th<sub>, η, U<sub>T<sub>, and I<sub>spec<sub> are the transistor model parameters for threshold voltage, slope factor, thermal voltage, device specific current respectively[^26]. This formulation allows the nonlinear signal compression to be estimated as \\(\epsilon\\) which is expanded in Eq. 3 to determine an appropriate ratio \\(\Delta\\)=I\tss{\\(\Delta\\)}/I<sub>B<sub> where IC=I<sub>B<sub>/I<sub>spec<sub>. Finally note the desirable property that the open-loop gain is inherently infinite and independent of any operating conditions. Moreover the digital output can virtually drive any type of load without affecting the circuit bandwidth.
$$ \epsilon = \frac{ V_{th} + \eta U_{T} \: ln[ 2 IC (1 + \Delta) ] }{ V_{th} + \eta U_{T} \: ln( 2 IC ) } - 1 $$
## 5 Two-Stage ROF
{{< figure src="/images/tcas2016/TD_L2.svg" title="Figure 4: The compensated two-stage ROF topology which uses the first order structure and introduces a more explicit pole due to the switched current and load capacitor C<sub>L<sub>. Shown are: (a) implementation; and (b) the s-domain equivalent as two ideal integrators in feedback." width="500" >}}
{{< figure src="/images/tcas2016/Bode-Plot.svg" title="Figure 5: Characteristic phase and magnitude response of the two-stage ROF structure with capacitive compensation." width="500" >}}
The two-stage ROF structure is shown in Fig. 4. This provides more degrees of freedom in the design with a small increase in complexity over the single-stage ROF. The main difference here is that a more conventional charge pump now precedes the oscillator and is responsible for the filtering characteristics. By having the digital output drive the capacitor C<sub>L<sub> the TD integrator is both compensated and able to operate at maximum efficiency irrespective of oscillator frequency. The s-domain coefficients are therefore k1 = I\tss{\\(\Delta\\)}/C<sub>L<sub> and k2 = gm<sub>MB<sub>/q<sub>max<sub>. The factor C in Fig. 4 accounts for the total capacitance C<sub>T<sub> on V\tss{P/N} that may attenuate the feedback by defining it as C = C<sub>L<sub>/C<sub>T<sub> and gm<sub>MB<sub> is the transconductance of the biasing transistor M<sub>B<sub>. This means that bandwidth efficiency of the VCO integrator is now boosted by the transistor's sub-threshold slope 1/η U<sub>T<sub>. The requirement of f<sub>osc<sub> in fact becomes relaxed and may actually be smaller than the circuit's bandwidth if multiple phases are used to represent Q in parallel denoted as K.
The impact of processing multiple taps from the ring oscillator is two-fold. First the stability requirement for the VCO pole location to lie outside the circuit bandwidth f<sub>3dB<sub> = k1 /2π generally becomes negligible as it is easy to guarantee k1\textless C K k2. This condition implies that the loop has a phase-margin \textgreater 45\tps{\\(\circ\\)} when the two pole structure is put in unity-gain configuration. Secondly the combined value of Q will in effect have K+1 quantisation levels that due to the capacitive feedback onto V\tss{P/N} presents high frequency quantisation noise with an amplitude of V<sub>DD<sub>/K. Similarly to the previous linearity requirement regarding I\tss{\\(\Delta\\)}/I<sub>B<sub>, K should intentionally be large to obtain linear behaviour of M<sub>B<sub> and the oscillators. Fortunately K does not affect the efficiency or power dissipation of this circuit as the product of K f<sub>osc<sub> is a constant for a fixed current in I<sub>MB<sub>. Instead K influences circuit complexity to some extent. Another benefit of the two-stage configuration is that although the band-limiting capacitor needs to be broken up into K units to accommodate all phases it is an explicit capacitor and unlike the single-stage configuration it does not rely on the precise control/matching of parasitic capacitance to determine the pole location. Moreover charge pump circuits and the associated dynamics have been studied extensively in PLL circuits[^27] and can easily be applied here. That said, it can be concluded that the two-stage ROF should be used in scenarios when the output and bandwidth characteristics need to be precise and the single-stage ROF should be applied when focus lies with performing asynchronous computation with diminished requirements.
$$ H(s) = \frac{k1 k2}{s^2+C k2 s} \cdot e^{-s t_d} $$
The open loop system response with capacitive compensation is characterised by Eq. 4. This is derived using the linearised model and introducing the impact of digital gate delay (t<sub>d<sub>) for further processing Q to the frequency response[^10]. The corresponding Bode plot is shown in Fig. 5. The second order roll-off will assist in rejecting high frequency artefacts due to any approximations made in the digital processing system. It should also be evident from the linearised model that high pass behaviour can be realised with the same feedback but instead taking the output from the digital processing block which is driving the charge-pump circuit.
# 6 Digital Processing using ROFs
From the introduction it is clear that there is large variety of techniques being used to process time domain signals with asynchronous logic. This section will present specific techniques for manipulating the multi-phase PWM signals that can be obtained from the ROF without introducing delay lines. Applying Boolean functions to PWM signals can be divided into two scenarios: coherent and incoherent operation. This relates to the cases when the signals being operated on are the exact same frequency (e.g. different phases of the oscillator) or when they are different frequencies (e.g. when processing the signals D & Q). It will be shown that these two cases lead to significantly different behaviour.
## 7 Coherent Operations
{{< figure src="/images/tcas2016/TDC_1.svg" title="Figure 6: Average PWM output for simple Boolean functions with a coherent input. The output is evaluated with respect to the pulse width of A and the delay \\(\Delta\\)T." width="500" >}}
{{< figure src="/images/tcas2016/TDC_2.svg" title="Figure 7: Average PWM output and the analytical result for a gain of 2x (blue), gain of 4x (green), and the complement of the absolute value for x-0.5 with the exact Boolean operator **B** annotated." width="500" >}}
The coherent operations useful for manipulating the multiple phases output by a single ring oscillator because these delays are relatively well matched with respect to the oscillator period, thereby allowing predictable outputs irrespective of oscillator frequency. These simple operations are summarised in Fig. 6. This visualises the average PWM output Q subject to a PWM input A, the delay \\(\Delta\\)T and a Boolean function **B**. Here A is a periodic function with a normalised periodicity of one. As expected Q is linear with respect to the pulse width x of A. Let A be formally defined in terms of Eq. 5 such that Q can be evaluated as Eq. 6. This calculates the mean value of Q over the period of A denoted as T.
$$ A(\tau,x) =\begin{cases} 1 & \tau (mod\: 1) \: < \:x 0 & \text{otherwise} \end{cases} $$
$$ E[Q(x,\Delta T)] = \int_{0}^{1} \mathbf{B}(A(\tau,x),A(\tau-\Delta T,x)) \: d\tau $$
However most of these operations can be visualised in terms of adding and removing pulses using delayed components of A. For instance using an OR gate with a delay of 0.5T will add an identical pulse at half the period and realise the equivalent 'gain' of 2x and effectively doubling the frequency of A. This example also illustrates that clipping will occur if x exceeds 0.5T as a natural consequence of overflow/saturation. Note that the output of **B** for the AND and OR gates have 3 regions that exhibit saturation, linear dependency, or gain. The interesting aspect here is that the point of clipping can be chosen freely by closely inspecting the region in Fig. 6 for which **B** is always 1. An underflow will occur for a pulse width smaller than c when using an AND gate with a delay of cT and an overflow will occur for a pulse width larger than (1-c) if an OR gate is used with a delay of cT. The clipping regions will not exceed 0.5 unless we combine more phases to realise larger 'gain' factors as illustrated in Fig. 7.
## 8 Incoherent Operations
{{< figure src="/images/tcas2016/TDG_1.svg" title="Figure 8: Average PWM output for simple Boolean functions with incoherent inputs A & B. The output is evaluated with respect to the pulse width of each input." width="500" >}}
{{< figure src="/images/tcas2016/TDG_2.svg" title="Figure 9: The result from applying an AND gate(blue), OR gate (green), and XOR gate (red) to two PWM signals with equal pulse width but are modulated by different frequencies with the analytical polynomial annotated as a function of pulse width x." width="500" >}}
Typically it will be the case that the signals of interest will not have the same frequency which requires us to consider how the two PWM signals A & B interact with one another. The primary interest will still lie with the average or near-DC behaviour of the Boolean function because the ROF is inherently lowpass in response. The main concern is associated with the beat frequency of the two PWM carrier frequencies f<sub>A<sub>-f<sub>B<sub>. This is because this spur needs to lie sufficiently outside of the f<sub>3dB<sub> bandwidth for us to make the approximation that B is uncorrelated with respect to A. This implies that the pulse B can be assumed uniformly distributed with respect to A. The circuit bandwidth will represent the averaging time constant and should ideally not be subject to carrier dependent tones such that a precise output is maintained. The oscillator frequencies are easily perturbed and subject to drift making this assertion quite reasonable in practice. As a result the average output Q due to two PWM signals with pulse width x & y can be calculated using the expression in Eq. 7.
$$ E[Q(x,y)] \approx \int_{0}^{1} \int_{0}^{1} \mathbf{B}(A(\tau,x),B(t-\tau,y)) \: d\tau dt $$
This type of processing uses concepts from stochastic computation \cite{SDSP, sto_cmp} since the two digital signals interact with respect to a probability distribution that is shaped using the Boolean operator. The difference however is that these bitstreams themselves are not stochastic in the large signal sense and they are not clocked by some specific frequency. Instead the bitstreams are intentionally decorrelated by choosing different carrier frequencies. The primitive operations are summarised in Fig. 8 with respect to the PWM signals A and B. In some cases these operations will lead to nonlinear or polynomial behaviour which can be observed in Fig. 9. In addition the inverse of these functions can also be realised by manipulating the feedback and using **B**(Q,R) instead of Q directly where R is the output of a single-stage ROF in unit gain feedback with the input Q but the carrier frequency is doubled to decorrelate R from Q.
# 9 Circuit Implementation
\begin{figure*}
\centering
\includegraphics[width=18cm]{/images/tcas2016/System.svg}
\caption{Detailed transistor level implementation of the second-order ROF structure. Here the digital gates in: (a) implement a difference operator; (b) is the switched current DAC; (c) is the floating differential ring oscillator structure; (d) is the differential delay cell, and (e) is the corresponding buffer that amplifies the oscillator voltage to full swing. All device sizes are shown in (f). }
\label{Fig:TDSys}
\end{figure*}
This particular implementation focuses on achieving robust low-voltage operation and minimising analogue complexity to enable larger multi-channel systems. A commercially available TSMC 65 nm CMOS LP MS RF technology (1P9M 6X1Z1U RDL) was used to develop a lowpass filter that processes the signals from the TD instrumentation circuit in [^30] and illustrates the basic performance characteristics of the ROF structure. The proposed circuit is detailed in Fig. \ref{Fig:TDSys} which can be divided into four sub-blocks: digital control (a), analogue integrator (b), TD integrator (c), and the oscillator stages (d & e).
## 10 Charge Pump
The switches S\tss{A/B/C} control how a reference current I<sub>B<sub> is pumped differentially into nodes V\tss{P/N}. Transistors M\tss{1-2} provide common mode regulation on V\tss{P/N} and mirrors the biasing current into the ring oscillators using M\tss{3-4}. This is extended for multi-phase inputs by operating several charge pumps in parallel. Any resulting voltage difference across V\tss{P/N} injects a differential current into the TD integrator as M\tss{3-4} represent a pseudo-differential pair. Although it is not shown M\tss{3-4} is split up into 5 devices of which two have their drain connected to the opposite polarity which allows us to manipulate the I\tss{\\(\Delta\\)}/I<sub>B<sub> ratio. This leads to a smaller VCO bandwidth and induces more filtering with better linearity. Using high V<sub>th<sub> devices for M\tss{1-4} allows the common mode of V\tss{P/N} to be placed close to 250 mV which leaves enough voltage headroom for the switches and biasing transistors.
{{< figure src="/images/tcas2016/ISF.svg" title="Figure 10: Post-layout simulation results showing to one of the oscillator outputs in a) for reference and the ISF \\(\Gamma_{ig}\\),\\(\Gamma_{io}\\),\\(\Gamma_{ir}\\) for injecting a small signal charge at the virtual ground, oscillator output, and virtual rail nodes." width="500" >}}
## 11 Differential Oscillator
Each oscillator consists of 7 differential delay stages each of which use a cross coupled load resulting in a total of 14 outputs. This structure is based on [^31] to achieve additional supply noise rejection when compared to the conventional ring oscillator. The 5 nA biasing current for each charge pump will lead to sub-threshold operation of all analogue devices which means the oscillator output that swings around V<sub>R<sub> & V<sub>G<sub> is only 100 mVpp with a transition time of 1/(14 f<sub>osc<sub>). Amplifying this output to improve signal transition time with high efficiency is achieved by a buffer that recovers the digital signal integrity and also uses positive feedback provided by M\tss{16-17}. This particular configuration requires some consideration with respect to the the optimal operating conditions of the buffer.
The charge sensitivity for this oscillator is shown in Fig. 10. The ISF has been extracted using using post-layout simulation results. The sensitivities \\(\Gamma_{ig}\\), \\(\Gamma_{ix}\\), and \\(\Gamma_{ir}\\) are evaluated by injecting 1 fC of charge \\(\Delta\\)Q into the nodes V<sub>GP<sub>, V<sub>OP<sub>, V<sub>R<sub> and evaluating the change in phase with respect to having no charge injected. Then \\(\Gamma\\) is characterised by systematically injecting charge at some point in time (t<sub>q<sub>) with respect to the oscillator period and performing normalisation as \\(\Gamma\\)(tq)=2π \\(\Delta\\)φ(t<sub>q<sub>) f<sub>osc<sub>/\\(\Delta\\)Q to obtain the small signal equivalent. This illustrates the phase independent characteristic of \\(\Gamma_{ir}\\) as well as the 100 mV swing of the oscillator. Note that noisy aggressors coupled through \\(\Gamma_{ir}\\) are common to both phase outputs and rejected by the low impedance from M<sub>5<sub>. The behaviour of \\(\Gamma_{ix}\\) is also interesting because when the output is not transitioning the coupling is shorted to either virtual supply and therefore has equivalent sensitivity. However during a transition there is a brief doubling sensitivity as it is being injected into one node instead of being loaded by the differential structure. It should be noted that \\(\Gamma_{ix}\\) is not very representative for modelling how noise couples at the output since many sources will be psuedo-common to all stages (e.g. substrate noise) and the transistor noise is further affected by the operating point of the device itself.
## 12 TDFA unit
The PWM difference operator or time-domain full-adder (TDFA) unit is detailed more clearly in Fig. 11. This shows that a crucial aspect of computing with incoherent TD signals lies with carefully using different signal representations. In this case the nonlinearity that would have been expected from Sec. 8 is negated by using a 1.5 bit ternary encoding. Instead the output Q is linearly dependent on the difference in pulse width of D & Q without distortion. This is important because in-band distortion is not shaped by the filter and any nonlinearity from **B** will propagate to the output including down modulated PWM carrier spurs.
{{< figure src="/images/tcas2016/TDFA.svg" width="500" >}}
{{< figure src="/images/tcas2016/SUM.svg" title="Figure 11: Implementation of the linearised TDFA unit which calculates the difference with respect to the two PWM encoded signals D & Q." width="500" >}}
## 13 Fabricated Prototype
The fabricated device is shown in Fig. 12. This prototype integrates a number of TD sensing systems together where the TD ROF structure is located in the lower left section. This subsystem operates together with an asynchronous analogue to time converter (ATC) such that the measured characterisation reflects system-level performance. Moreover this mitigates any difficulty associated with precisely generating PWM encoded signals off-chip and transmitting them to the filter under low noise conditions. The entire system is 7200 μ m² in size and one ROF is around 30\\(\times\\)40 μ m². Excluding the ATC this filter structure has a 3600 μ m² silicon footprint. There is also a reconfigurable asynchronous DSP block that realises several different coherent Boolean operations intermediate to the ATC and ROFs blocks. In particular there are variable-gain blocks that use the gain function from Sec. 7.
{{< figure src="/images/tcas2016/chip_fab.svg" title="Figure 12: Microphotograph of the fabricated device showing the chip with annotated floor plan in (a) while the P1,M1,M2 layers of the ROF layout are highlighted in (b) (n.b. metal fill omitted for clarity)." width="500" >}}
# 14 Measured Results
{{< figure src="/images/tcas2016/setup.svg" title="Figure 13: Experimental setup used for characterising the ROF filters. Various off-chip instruments are used to supply power and analogue test signals to the device while a Saleae Logic digital acquisition tool samples the PWM output from the chip." width="500" >}}
{{< figure src="/images/tcas2016/pcb.svg" title="Figure 14: Photograph of the custom printed circuit board used for testing the ASIC." width="500" >}}
## 15 Experimental Setup
A custom test platform was developed to characterise the fabricated ASIC using Raspberry Pi 3 development board to provide a graphical interface that automates the low level device control and test routines. This setup is illustrated in Fig. 13 with a photograph of the custom PCB in Fig. 14. The SPI interface allows the hardware to be reconfigured using a configuration register where 3 bits are used to fine tune the biasing current I<sub>B<sub> and another 10 bits are used for variable gain (VG) settings and output control. As shown the ROF signal chain consists of 6 blocks in the following order: ATC, VG, ROF, VG, MUX. The ATC will sense and amplify 5 mVpp differential signals and generate a PWM encoded signal with a 450 kHz carrier frequency. The VG blocks can select additional X1-X4 gain settings using only digital logic. The cascaded ROF provides a 4th order lowpass filter and the MUX gives control over which signals are sent off chip. Not all the TD phases will be sent off chip because of noise and overhead concerns. Instead the MUX will output one phase from the ATC or ROF for preliminary characterisation during asynchronous operation. The digital bit stream appearing at the output is then acquired at 100 MS/s over 1 second using a digital scope.
{{< figure src="/images/tcas2016/spec.svg" title="Figure 15: Spectral power densities of the ROF PWM output with a 4 mVpp 1 kHz differential input signal where the distortion has been annotated in red and the oscillator harmonics are annotated in blue." width="500" >}}
## 16 Filter Characteristics
Taking the Fourier transform of the PWM output gives the spectrum shown in Fig. 15. Here the ROF oscillator frequency is observed at around 35 kHz with the corresponding higher harmonics. The bandwidth of this filter was designed to be 5 kHz which means these aggressors are sufficiently rejected for most applications. In fact the measured filter response in Fig. 16 shows the cascaded ROF will reject these harmonics by more than 50 dB. More practically, when the output of the ROF output needs to be sampled without the interference of such harmonics, this structure can easily be transformed into an oversampling TDC that decimates the PWM signal and filters out of band components [^17][^30]. This particular setup uses a 5.2 nA biasing current which leads to the charge-pump pole being precisely situated at the 5 kHz. Because the VCO pole location suffers from increased variability it is intentionally placed at twice the charge-pump cut-off frequency. It is evident from Fig. 16 that verifying the post-fabrication pole position and the corresponding variance remains challenging. If necessary this pole location can be calibrated using established techniques such as trimming M\tss{3-4} or introducing a digitally-switched capacitive load [^32] at the cost of increasing circuit complexity.
## 17 Linearity
Using a 1 kHz tone, the linearity characteristics are shown in Fig. 17. It is important to note that the use of an on-chip ATC implies that the distortion also includes nonlinearity from the amplifying ATC. The signal processing chain can accept a maximum input 4 mVpp under before the ATC feedback loop starts to overload the asynchronous \\(\Delta\Sigma\\) modulator. These measurements show that a maximum total harmonic distortion (THD) and spurious-free dynamic range SFDR of 53 dB is achievable for a 0.6 mVpp input amplitude. The noise floor is slightly higher than -80 dB and calculating the integrated noise over 10 kHz indicated that the maximum SNR is 55 dB for a 4 mVpp input signal that has a THD of 44 dB. In order to minimise the impact of ATC nonlinearity a 2x VG setting is used during this test such that the ATC output is at -4 dB of the full range but the ROF processes signals near the full input dynamic range.
## 18 Supply Noise Sensitivity
The PSRR has been tested using a 10 mVpp tone at different frequencies while the ATC input was shorted together. The result is presented in Fig. 18. This perturbation induces output tones at -55 dB of the full range which when referred to the 4 mV input range implies a PSRR of 63 dB. This level of supply coupling is difficult to improve because of this measurement setup and the ADC nature of the ATC. The implementation of the ATC uses V<sub>DD<sub> as reference voltage such that it is coupled asymmetrically to analogue nodes degrading supply rejection even in differential configurations. Although the impact of using the differential oscillator structure is not well represented, any further degradation in PSRR is prevented and the input referred noise-floor is not corrupted by supply noise coupled from the digital switching. Moreover this figure should be very representative for larger scale or multi channel systems as this implementation only uses a 2.5 pF decoupling capacitor for the shared 0.5 V supply. It can thus be expected that using more decoupling capacitance or separating the supplies will further improve this figure at the cost of allocating more resources.
{{< figure src="/images/tcas2016/measure.svg" title="Figure 16: Measured filter response due to a 4 mVpp differential sinusoidal input at frequencies from 1 kHz to 100 kHz." width="500" >}}
{{< figure src="/images/tcas2016/THD1.svg" title="Figure 17: Measured harmonics due to a 1 kHz differential input tone with increasing input amplitudes. The spectral power of the output tones are calculated with respect to the maximum output dynamic range." width="500" >}}
{{< figure src="/images/tcas2016/PSRR.svg" title="Figure 18: Measured PSRR of the entire system due to a 10 mVpp sinusoidal signal on top of a 0.5 V bias driving the system's V<sub>DD<sub> at frequencies from 50 Hz to 60 kHz." width="500" >}}
## 19 Performance Summary
Table 1: System Characteristics and Comparison with State-of-the-Art
| Parameter [unit] |\textbf{\small{This Work}} | [^13](^\ddagger) | [^6] | [^10] | [^17]\cite{1} | [^20] | [^34] |
|----|----|----|----|----|----|----|----|
| Tech.[nm] | **65** | 130 | 90 | 65 | 40 | 130 | 180 |
| Modality | **Time** | Time | Time | Time | Time | Volt. | Volt. |
| Type | \textbf{TD-IIR} | TD-FIR | TD-IIR | TD-IIR | TD-(\Delta\Sigma) | GmC-(\Delta\Sigma) | GmC-IIR |
| Order | **4** | 16 | 4 | 4 | 2 | 1 | 5 |
| Supply-V[V] | **0.5** | 1 | 0.55 | 0.6 | 0.9 | 0.25 | 0.5 |
| Supply-I[A] | **146 n** | 0.46 m | 5.27 m | 43.7 m | 2.8 m | 72 n | 1.2 m |
| Bandwidth[Hz] | **5 k** | 70 k | 7 M | 70 M | 40 M | 1.9 k | 135 k |
| DR[dB] | \textbf{55(\dagger)} | 50 | 61 | 58 | 61 | 58 | 61 |
| Area[mm²] | **0.004** | 5 | 0.29 | 0.38 | 0.017 | 0.08(^\star) | 0.29 |
| FOM[fJ/pole] | **8.17** | 1299 | 92 | 118 | 28 | 12 | 520 |
{\thanks{\\(\dagger\\) using a 10 kHz integrated noise figure, \\(^\ddagger\\) performance quote from full system asynchronous PWM operation, \\(^\star\\) uses external passive components.}}
The filter performance is summarized in Table 1. The circuit power consumption has been measured to be 73 nW of which simulation results indicate 16 nW is dissipated in the charge pump plus oscillator circuits and 21 nW is dissipated by the biasing circuits. The remaining 36 nW is due to digital control and PWM switching. One of these contributions comes from applying digital feedback onto the capacitor C<sub>L<sub> which is 560 fF. This is expected to dissipate power according to f<sub>osc<sub>C<sub>L<sub>V²<sub>DD<sub> or in this particular case 3 nW. This later component can be become substantial if the supply voltage is not small enough or if very low-noise performance is required since in-band noise performance is directly dependent on C<sub>L<sub>. However when compared to other works the achieved performance is comparable and can operate with good energy efficiency. This is evaluated using the FOM from [^34] which is defined in Eq. 8 using the system power (P<sub>sys<sub>) and the number of poles (N<sub>poles<sub>) to normalise performance. The most substantial gain from the ROF filter is that the reduced complexity leads to a very compact implementation that is not only considerably smaller than state-of-the-art but also more capable of reconfigurable functionality. Based on KT/C relations we may expect all-analogue processing to be more power efficient in a noise limited scenario because such systems can take advantage of the transistor sub-threshold slope. This drawback is similar to the noise performance from all-digital PLLs in comparison to sub-sampling PLLs. However the time-domain circuits will allow far superior linearity & dynamic range during ultra low voltage operation which the all-analogue systems cannot achieve. The 65 nm technology primarily influences the impact of excess digital switching from the asynchronous logic/overhead. Using an advanced CMOS technology allows most of the power to be dissipated in the oscillator and enables more efficient performance.
$$ FOM = \frac{P_{sys}}{N_{poles} f_{3dB} DR} $$
# 20 Conclusion
This work presents the first system to explicitly deliver IIR or analogue filtering for PWM encoded signals asynchronously using standard CMOS technology. The implementation and model of a low-complexity oscillator based filter is detailed to complement existing FIR and delay line based techniques for clockless processing of time-encoded signals. The proposed topology can deliver 53 dB SFDR with a maximum SNR of 55 dB while operating at 0.5 V. The extensive use of digital logic allows highly flexible and reconfigurable oscillator based computing for future ultra-low-power systems in nanometre CMOS. Measured results demonstrate 8.17 fJ/pole efficiency for the 5 kHz bandwidth and reports an area requirement of 0.004 mm² . In fact unlike prior art this topology is substantially more efficient and compact at processing asynchronous TD signals that have reduced bandwidths or require low frequency filtering than state-of-the-art. Moreover the ROF primitives and digital processing techniques presented here can be directly applied to ultra-low-power \\(\Delta\Sigma\\) modulators and mixed signal systems due to its simplicity and affinity for low voltage mixed signal operation.
# 21 Acknowledgement
The authors would like to thank Dr. Pantelis Georgiou, and the Europractice Advanced Technology Stimulation programme for providing access to the TSMC 65nm technology. The authors additionally thank Michal Maslik for the helpful comments and assistance with improving this manuscript.
# Refernces:
[^1]: I.L. Markov, ''Limits on fundamental limits to computation,'' Nature, vol. 512, pp. 147--154, August 2014. [Online]: http://dx.doi.org/10.1038/nature13570
[^2]: R.Sarpeshkar, ''Analog versus digital: Extrapolating from electronics to neurobiology,'' Neural Computation, vol.10, no.7, pp. 1601--1638, Oct 1998. [Online]: http://dx.doi.org/10.1162/089976698300017052
[^3]: N.Guo etal., ''Energy-efficient hybrid analog/digital approximate computation in continuous time,'' IEEE Journal of Solid-State Circuits, vol.51, no.7, pp. 1514--1524, July 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2543729
[^4]: M.Verhelst and A.Bahai, ''Where analog meets digital: Analog-to-information conversion and beyond,'' IEEE Solid-State Circuits Magazine, vol.7, no.3, pp. 67--80, September 2015. [Online]: http://dx.doi.org/10.1109/MSSC.2015.2442394
[^5]: Y.Chen, E.Yao, and A.Basu, ''A 128-channel extreme learning machine-based neural decoder for brain machine interfaces,'' IEEE Transactions on Biomedical Circuits and Systems, vol.10, no.3, pp. 679--692, June 2016. [Online]: http://dx.doi.org/10.1109/TBCAS.2015.2483618
[^6]: B.Drost, M.Talegaonkar, and P.K. Hanumolu, ''Analog filter design using ring oscillator integrators,'' IEEE Journal of Solid-State Circuits, vol.47, no.12, pp. 3120--3129, Dec 2012. [Online]: http://dx.doi.org/10.1109/JSSC.2012.2225738
[^7]: G.W. Roberts and M.Ali-Bakhshian, ''A brief introduction to time-to-digital and digital-to-time converters,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.57, no.3, pp. 153--157, March 2010. [Online]: http://dx.doi.org/10.1109/TCSII.2010.2043382
[^8]: T.Anand, K.A.A. Makinwa, and P.K. Hanumolu, ''A vco based highly digital temperature sensor with 0.034 $^\circ$C/mV supply sensitivity,'' IEEE Journal of Solid-State Circuits, vol.51, no.11, pp. 2651--2663, Nov 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2598765
[^9]: V.Pourahmad etal., ''Nonboolean pattern recognition using chains of coupled cmos oscillators as discriminant circuits,'' IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol.3, pp. 1--9, Dec 2017. [Online]: http://dx.doi.org/10.1109/JXCDC.2017.2654300
[^10]: B.Vigraham, J.Kuppambatti, and P.R. Kinget, ''Switched-mode operational amplifiers and their application to continuous-time filters in nanoscale cmos,'' IEEE Journal of Solid-State Circuits, vol.49, no.12, pp. 2758--2772, Dec 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2354641
[^11]: S.Zheng and H.C. Luong, ''A wcdma/wlan digital polar transmitter with low-noise adpll, wideband pm/am modulator, and linearized pa,'' IEEE Journal of Solid-State Circuits, vol.50, no.7, pp. 1645--1656, July 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2413846
[^12]: P.Lu, Y.Wu, and P.Andreani, ''A 2.2-ps two-dimensional gated-vernier time-to-digital converter with digital calibration,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.63, no.11, pp. 1019--1023, Nov 2016. [Online]: http://dx.doi.org/10.1109/TCSII.2016.2548218
[^13]: C.Vezyrtzis etal., ''A flexible, event-driven digital filter with frequency response independent of input sample rate,'' IEEE Journal of Solid-State Circuits, vol.49, no.10, pp. 2292--2304, Oct 2014. [Online]: http://dx.doi.org/10.1109/JSSC.2014.2336532
[^14]: H.J. Kwon etal., ''Analysis of an open-loop time amplifier with a time gain determined by the ratio of bias current,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.61, no.7, pp. 481--485, July 2014. [Online]: http://dx.doi.org/10.1109/TCSII.2014.2328800
[^15]: W.Yu, K.Kim, and S.Cho, ''A 0.22 ps rms integrated noise 15 mhz bandwidth fourth-order $\Delta \Sigma$ time-to-digital converter using time-domain error-feedback filter,'' IEEE Journal of Solid-State Circuits, vol.50, no.5, pp. 1251--1262, May 2015. [Online]: http://dx.doi.org/10.1109/JSSC.2015.2399673
[^16]: W.Jiang etal., ''A ±50 mV linear-input-range vco-based neural-recording front-end with digital nonlinearity correction,'' IEEE Journal of Solid-State Circuits, vol.52, no.1, pp. 173--184, Jan 2017. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2624989
[^17]: M.Hovin etal., ''Delta-sigma modulators using frequency-modulated intermediate values,'' IEEE Journal of Solid-State Circuits, vol.32, no.1, pp. 13--22, Jan 1997. [Online]: http://dx.doi.org/10.1109/4.553171
[^18]: Y.Liu, J.L. Pereira, and T.G. Constandinou, ''Clockless continuous-time neural spike sorting: Method, implementation and evaluation,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2016, pp. 538--541. [Online]: http://dx.doi.org/10.1109/ISCAS.2016.7527296
[^19]: M.Yang etal., ''A 0.5 v 55 $\mu$w 64$ imes$2 channel binaural silicon cochlea for event-driven stereo-audio sensing,'' IEEE Journal of Solid-State Circuits, vol.51, no.11, pp. 2554--2569, Nov 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2604285
[^20]: L.H.C. Ferreira and S.R. Sonkusale, ''A 0.25-V 28-nW 58-dB dynamic range asynchronous delta sigma modulator in 130-nm digital cmos process,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.23, no.5, pp. 926--934, May 2015. [Online]: http://dx.doi.org/10.1109/TVLSI.2014.2330698
[^21]: R.Mohan etal., ''A 0.6 V, 0.015-mm$^2$, time-based ecg readout for ambulatory applications in 40 nm cmos,'' IEEE Journal of Solid-State Circuits, vol.52, no.1, pp. 298--308, Jan 2017. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2615320
[^22]: S.Patil etal., ''A 3-10 fJ/conv-step error-shaping alias-free continuous-time adc,'' IEEE Journal of Solid-State Circuits, vol.51, no.4, pp. 908--918, April 2016. [Online]: http://dx.doi.org/10.1109/JSSC.2016.2519396
[^23]: J.P. Caram, J.Galloway, and J.S. Kenney, ''Harmonic ring oscillator time-to-digital converter,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2015, pp. 161--164. [Online]: http://dx.doi.org/10.1109/ISCAS.2015.7168595
[^24]: W.-H. Ki, ''Signal flow graph analysis of feedback amplifiers,'' IEEE Transactions on Circuits and Systems---Part I: Fundamental Theory and Applications, vol.47, no.6, pp. 926--933, Jun 2000. [Online]: http://dx.doi.org/10.1109/81.852948
[^25]: A.Hajimiri, S.Limotyrakis, and T.Lee, ''Phase noise in multi-gigahertz cmos ring oscillators,'' in IEEE Proceedings of the Custom Integrated Circuits Conference, May 1998, pp. 49--52. [Online]: http://dx.doi.org/10.1109/CICC.1998.694905
[^26]: ibitemQ-basedC.C. Enz and E.A. Vittoz, Charge-based MOS transistor modeling: the EKV model for low-power AND RF IC design.\hskip 1em plus 0.5em minus 0.4em
elax John Wiley & Sons, August 2006. [Online]: http://eu.wiley.com/WileyCDA/WileyTitle/productCd-0470855452.html
[^27]: A.Homayoun and B.Razavi, ''On the stability of charge-pump phase-locked loops,'' IEEE Transactions on Circuits and Systems---Part I: Regular Papers, vol.63, no.6, pp. 741--750, June 2016. [Online]: http://dx.doi.org/10.1109/TCSI.2016.2537823
[^28]: D.Jenson and M.Riedel, ''A deterministic approach to stochastic computation,'' in IEEE Proceedings of the International Conference on Computer-Aided Design, Nov 2016, pp. 102:1--102:8. [Online]: http://dx.doi.org/10.1145/2966986.2966988
[^29]: M.Alawad and m.lin, ''Survey of stochastic-based computation paradigms,'' IEEE Transactions on Emerging Topics in Computing, vol.PP, no.99, pp. 1--1, 2016. [Online]: http://dx.doi.org/10.1109/TETC.2016.2598726
[^30]: L.B. Leene and T.G. Constandinou, ''A 0.5V time-domain instrumentation circuit with clocked and unclocked $\Delta\Sigma$ operation,'' in IEEE Proceedings of the International Symposium on Circuits and Systems, May 2017, pp. 2619--2622.
[^31]: W.S.T. Yan and H.C. Luong, ''A 900-MHz cmos low-phase-noise voltage-controlled ring oscillator,'' IEEE Transactions on Circuits and Systems---Part II: Analog and Digital Signal Processing, vol.48, no.2, pp. 216--221, Feb 2001. [Online]: http://dx.doi.org/10.1109/82.917794
[^32]: Y.Zhang etal., ''A 0.35-0.5 V 18-152 MHz digitally controlled relaxation oscillator with adaptive threshold calibration in 65 nm cmos,'' IEEE Transactions on Circuits and Systems---Part II: Express Briefs, vol.62, no.8, pp. 736--740, Aug 2015. [Online]: http://dx.doi.org/10.1109/TCSII.2015.2433531
[^33]: X.Xing and G.G.E. Gielen, ''A 42 fj/step-fom two-step vco-based delta-sigma adc in 40 nm cmos,'' IEEE Journal of Solid-State Circuits, vol.50, no.3, pp. 714--723, March 2015.