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title: "A 890 fj bit UWB Transmitter for SOC Integration in High Bit-Rate Transcutaneous Bio-Implants"
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date: 2013-05-19T15:26:46+01:00
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draft: false
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toc: true
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type: posts
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math: true
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tags:
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- publication
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- wireless
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- CMOS
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- biomedical
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- telemetry
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---
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Lieuwe B. Leene, Song Luan, Timothy G. Constandinou
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Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
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Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
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# 1 Abstract
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The paper presents a novel ultra low power UWB transmitter system for near field communication in transcutaneous bio-telemetries. The system utilizes an all-digital architecture based on minimising the energy dissipated per bit transmitted by efficiently encoding a packet of pulses with multiple bits and utilizing oscillator referenced delays. This is achieved by introducing a novel bi-phasic 1.65 pJ per pulse UWB pulse generator together with a 72 μW DCO that provide a transmission bandwidth of 77.5 Mb/s with an energy efficiency of 890 fJ per bit from a 1.2 V supply. The circuit core occupies a compact silicon footprint of 0.026 mm² in a 0.18 μm CMOS technology.
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# 2 Introduction
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Since Pulsed Ultra Wide Band (UWB) technology has become available for unlicensed communication, a broad spectrum of ideas have been presented over the past decade with regard to UWB pulse modulation, generation and detection techniques[^1]. Recent literature has primarily demonstrated the potential all-digital UWB transmitters have in achieving ultra low power budgets by operating with aggressive duty cycles while maintaining substantial data rates. These developments are of considerable interest to biomedical applications, for example in neural interfaces estimates indicate that state-of-the-art systems already require data rates up to 40Mb/s without compression and a power budget of several mili-watt[^2]. Moreover, based on the recent projection regarding the steady exponential growth in number of neurons recorded[^3], we expect a considerable demand for a ultra low power wireless link that is capable of transmitting 80 Mb/s and is viable for integration on chip with the neural sensory devices in the coming years.
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The UWB transmitter presented here is based on developing a transcutaneous biotelemetry system where the transmitter is coupled to a receiver trough a near field communication channel across the skin boundary. The adoption of near field transmission for power and data is nearly ubiquitous in biotelemetry systems because it alleviates the challenge of coping with the lossy radiation environment of the human body and power restrictions due to thermal dissipation constraints. Moreover, near field communication should allow high SNR values with respect to interfering UWB devices such that a simple energy detection based receiver can fully detect the individual transmitted UWB pulses.
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This work presents an UWB transmitter architecture for asynchronous communication that achieves ultra low power consumption by minimising the energy dissipated per bit transmitted (EPB). This is achieved through circuit level optimizations in addition to encoding a packet of pulses with multiple bits. Furthermore scalable PPM modulation is achieved with significant improvements in both resource requirements and phase integrity over conventional techniques that either use a tuneable delay element or multiple delay lines[^4].
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This paper is organized as follows. Section 3 presents a discussion on the operation of the proposed architecture. Section 4 presents the transistor level implementations of a Digitally Calibrated Oscillator (DCO) and an novel UWB pulse shaper. Section 7 completes the design aspects of the transmitter by presenting the employed UWB antenna. Sections 8 & 13 demonstrate the performance of the proposed system and conclude upon this paper's findings.
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# 3 UWB Transmitter System Concept
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The system architecture of the UWB transmitter is shown in Fig. 1. This is based on using a DCO as a reference for the encoded delays intermediate to the pulse positions. This approach allows accurate definition of all relative pulse positions by calibrating a single element thereby reducing the system's resource requirement while maintaining scalability. The bi-phasic pulse generator extends this flexibility by allowing pulses to be modulated in terms of position and phase simultaneously.
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{{< figure src="/images/iscas2012/s1.png" title="Figure 1: System level architecture of the UWB Transmitter capable of M-arry PPM and BPSK modulation" width="500" >}}
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The PPM modulation mechanism relies on the removal or 'swallowing' of extraneous clock pulses generated by the DCO, hence introducing inter-pulse delays quantized by the DCO's period. This is achieved by disconnecting the power supply from the inter-stage buffer driving the pulse generator for specific intervals. These intervals are specified by a synchronized D flip-flop fed by a shift register with decisions to swallow or transmit the incoming pulse. Exact duty cycles are achieved by enabling the DCO on the rising edge of the input for a burst of clock cycles and disabling the DCO when the shift register detects the end of the pulse package.
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A high speed all-digital frequency locked loop is used on system start up to calibrate the DCO to a fixed oscillation frequency. Calibration is an important consideration as DCO frequency off-sets for this topology results in increasingly larger temporal off-sets for increasingly longer pulse packages and amounts to significant phase noise at the receiver.
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In order to maximize the efficiency of the transmitter, this system essentially cascades two delay-hopped time-reference (DHTR) pulse pairs where the second pulse is the reference pulse for the third pulse [^5]. The phase of each pulse is given by a 3-bit word, D<sub>2<sub> - D<sub>0<sub>. The implemented design allows the second pulse to be delayed to 8 different positions. The third pulse can then be delayed to 4 different positions with reference to the second pulse including a null position where the pulse is omitted. Note that when the third pulse is omitted standard DHTR modulation is achieved and the bit D0 is ignored. As a result each pulse package encodes 7.75 effective number of bits (ENOBs) with an average of 2.75 pulses per package for a equiprobable code book. The transmitted package may be represented analytically as
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$$ s(t)= a_{i} w(t) + b_{i} w(t - A_i \cdot T_{DCO}) + c_i w( t - (A_i + B_i) \cdot T_{DCO} ) $$
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where i is the package index, w(t) is the UWB pulse shape, and T<sub>DCO<sub> is the unit delay introduced by the DCO's period. a<sub>i<sub>, b<sub>i<sub>, c<sub>i<sub> in { +1, -1 } are the respective first, second, and third pulse phases. A<sub>i<sub> & B<sub>i<sub> are the respective delays of the first and second pulse pairs. Fig. 2 exemplifies two pulse packets with reference to the DCO clock whose encoding is given by; A<sub>1<sub>, B<sub>1<sub>, D(2-0)<sub>1<sub> = [010, 10, 010] and A<sub>2<sub>, B<sub>2<sub>, D(2-0)<sub>2 = [001, 01, 110].
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{{< figure src="/images/iscas2012/ex.png" title="Figure 2: Waveforms illustrating two different DHTR modulated pulse packages. a) DCO reference, b) package index 1 [010, 10, 010], c) package index 2 [001, 01, 110]$. " width="500" >}}
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# 4 Circuit Implementation
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The circuit has been implemented in a commercially available 0.18 μm CMOS technology provided by AMS/IBM (C18A4/7sf) and has been designed to operate from a 1.2 V supply. This section details the circuit level design and implementation.
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## 5 Digitally Calibrated Oscillator
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The DCO employed by the UWB transmitter is an 8-bit calibrated 5-stage ring oscillator as shown in Fig. 3. The five most significant bits of the calibration state C<sub>7<sub> to C<sub>3<sub> adjust the main capacitive load by shorting a select set of capacitors from a binary weighted array to ground and leaving others floating. The lower 3 bits C<sub>2<sub> to C<sub>0<sub> fine tune the oscillation frequency by adjusting the NMOS side driving capability of an the inverter stage achieving a resolution in the order of tens of pico-seconds by making fractional changes in aspect ratio for different matched transistors. Since the transistor 'on' resistance is inversely proportional to the tuned driving capability of the inverter, a 3-input look-up-table-based remapping is introduced. This improves the performance of the fine calibration bits by linearizing the tuneable delay with respect to the control bits. Note that the main delay elements are primarily dependent on the NMOS devices and the parasitic capacitance which by reducing the dependence on PMOS devices improves the sensitivity to process variation.
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{{< figure src="/images/iscas2012/s2.png" title="Figure 3: Circuit schematic of the 5-stage digitally calibrated Ring oscillator" width="500" >}}
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## 6 UWB Pulse Shaper
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The pulse shaper presented here has been partly adopted from previous work that used integrated LC components to filter out the unwanted spectrum to meet the FCC mask requirements[^6]. An integrated inductor is differentially pulsed with current over 180 ps which perturbs the LC resonator to start oscillating with the induced energy. This resonating energy is leaked towards the resistive load of the antenna over a longer time frame of 1ns. There is an explicit capacitive impedance mismatch at the bond-pad such that most of the energy induced by the driving transistors is fed into the inductor.
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The circuit consists of a two part design, including digital and RF sections. The Digital pre-shaper is shown in Fig. 4. This uses a popular glitch generator to generate 180ps long Gaussian like pulses, which are demultiplexed to two inverter chains to boost the driving capability of the output. It is important to note that these chains have a different output polarity but both output the buffered pulse together with a delayed and inverted pulse. The driving transistors in Fig. 5 source the inductor with pulsed current proportional to the glitch duration. The purpose of the delayed pulse is to cancel the DC component generated by the transient impulse response of the lossy LC resonator, by injecting an equal but complementary pulse at the opposite port of the inductor. By driving either the end connected to the load, or the C<sub>res<sub> end of the inductor first, the polarity of the UWB pulse is well controlled.
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The circuit shown in Fig. 4 also illustrates how a shift register can interface the UWB transmitter with a parallel input data stream. In the RF section (Fig. 5), it is interesting to note that since the transistor pairs M1, M4, M2, and M3 are matched in terms of driving capability this particular topology is immune to variations in pulse length. This would easily distort the output spectrum of aggressive UWB pulse generators that use multiple glitch generators to shape the pulse. The integrated 4 nH inductor is a single layer 6-turn 8-sided spiral with poly-silicon ground plane and dimensions 4 μm, 2.8 μm, 66 μm corresponding to the trace width, trace spacing, and outer radius respectively.
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{{< figure src="/images/iscas2012/s3.png" title="Figure 4: Circuit Schematic of the digital pre-shaping" width="500" >}}
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{{< figure src="/images/iscas2012/s4.png" title="Figure 5: Circuit schematic of the RF section with L = 4nH; C<sub>res<sub> = 200fF; - Note that the relative temporal delays of the driving signals are not to scale." width="500" >}}
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# 7 Miniaturized UWB Antenna
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An omni-directional UWB antenna that radiates in the plane of the skin boundary is used for near field coupling instead of an RF coil to reduce the potential interference from echos and other UWB sources. The antenna here is based on a generic elliptic co-planar mono-pole geometry which has been shown to have good non-dispersive radiation characteristics over the entire bandwidth[^7]. To assure that the radiated pulse meets the FCC requirements in the sub 2 GHz band, the antenna is required to reject this band by at least 20 dB with respect to the insertion loss in the 3.1 GHz - 10.6 GHz band.
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{{< figure src="/images/iscas2012/gg.png" title="Figure 6: Illustration of the antenna geometry and a high contrast photograph of a prototype next to a British pound with dielectric cover removed." width="500" >}}
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The antenna geometry is shown in Fig. 6, with the various antenna dimensions designed as follows; R = 5mm, R<sub>G<sub> = 400 μm, R<sub>T<sub> = 800 μm, G = 290 μm, W = 440 μm, C = 260 μm, t<sub>d<sub> = 635 μm, t<sub>m<sub> = 35 μm.
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The antenna uses an asymmetric extended ground plane to damp the first strong resonance that is usually centred around 3-4GHz and can introduce significant pulse distortion. To improve the viability of the antenna for an implanted system a high dielectric laminate with copper metallization, RO1030, was used on both sides of the metallization to scale down the dimensions to allow an off-chip imprint below 2 cm².
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# 8 Results
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The design was simulated in Cadence IC 5.141 ISR with foundry-supplied PSP models. This section details the DCO, pulse generator, antenna and system performance.
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## 9 Digitally Calibrated Oscillator
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Monte Carlo simulation revealed the proposed DCO has a standard deviation in oscillation frequency of 44.9 MHz. The calibration mechanism allows the DCO to sweep through from 750 MHz to 390 MHz with a resolution of approximately 4.5 MHz as shown in Fig. 7. The DCO consumes an average of 72 μW during continuous operation at 500MHz.
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{{< figure src="/images/iscas2012/swp.png" title="Figure 7: Transient simulation of the DCO sweeping through all calibration states" width="500" >}}
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## 10 Pulse Generator
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The transient simulation of the UWB pulse generator is illustrated in Fig. 8. This demonstrated a power dissipation of 1.65 pJ per pulse with a 344 mVpp Amplitude. Spectral analysis further shows a peak power spectral density of -50.6 dBm/MHz and FCC mask compliance over the 3.1 GHz - 10 GHz band.
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{{< figure src="/images/iscas2012/tr.png" title="Figure 8a: bi-phasic UWB temporal response." width="500" >}}
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{{< figure src="/images/iscas2012/dfs.png" title="Figure 8b: Simulated PSD of the designed UWB pulse & the indoor UWB FCC mask as annotated." width="500" >}}
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## 11 UWB antenna
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{{< figure src="/images/iscas2012/a1.png" title="Figure 9: Simulated reflection co-efficient S11 for the UWB antenna radiating in free space." width="500" >}}
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Preliminary EM simulations were carried out using CST MICROWAVE STUDIO package with a 50 ohm port impedance. Fig. 9 shows the UWB antenna achieves a -10 dB reflection over the 3.66 GHz to 7 GHz band without significant phase distortion.
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## 12 System Performance
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The complete system level simulation is shown in Fig. 10. This demonstrates the transmitter operating with a package frequency rate (PRF) of 20 MHz transmitting a 155 Mb/s bit stream of pseudo random data while consuming less than 40 pJ under 300 ns. For the target 10MHz PRF, the system consumes an average of 68.9 μW corresponding to a 890 fJ of energy dissipated per bit transmitted. The custom digital layout is shown in Fig. 11. This measures 135 μm by 60 μm excluding the 132 μm by 132 μm integrated inductor, giving a total core area of 0.026 mm².
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{{< figure src="/images/iscas2012/ps.png" title="Figure 10: Simulation result illustrating the voltage waveforms generated by the different components with a 20 MHz PRF and a random input data stream." width="500" >}}
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{{< figure src="/images/iscas2012/tx.png" title="Figure 11: Core Layout of the UWB transmitter with each block annotated as; a) UWB Pulse shaper b) Pulse Swallowing c) Serial Interface d) DCO." width="500" >}}
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# 13 Conclusion
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An all-digital UWB transmitter architecture has been presented for biomedical SOC integration that seeks to improve system efficiency by achieving asynchronous ultra low power operation for arbitrary bit rates. A DCO based modulation scheme is introduced that significantly reduces the on-chip resource requirements for PPM modulation and allowed efficient 8-bit encoding onto 3 UWB pulses. The novel low power bi-phasic UWB pulse generator further allows this system to achieve 890 fJ EPB on a 0.18 μm CMOS process to make integration with state of the art neural interfaces viable. The overall system achieves very aggressive performance in terms of power consumption for 10MHz PRF as illustrated in table 1. Future work will focus on tuning the UWB antenna to match the tissue impedance and characterizing the near field communication channel.
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Table 1: Performance overview of recent UWB transmitters
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|Reference | [^8] | [^9] | [^10] | [^11] | [^12] | This Work |
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|----|----|----|----|----|----|----|
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|Tech. (nm) | 65 | 130 | 65 | 65 | 65 | 180 |
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|Modulation | DHTR | BPSK | PPM | OOK | BPSK | DHTR |
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|Power (W) | 660n | 3.3m | 820u | 217u | 4.36m | 68.9u |
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|PRF (Hz) | 0.6M | 100M | 50M | 24M | 15.6M | 10M |
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|EPB (J/bit) | 300f | 33p | 12p | 8.5p | 17.5p | 890f|
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|FCC compliant | - | Yes | Yes | Yes | Yes | Yes |
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# Refernces:
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[^1]: A.Chandrakasan, F.Lee, D.Wentzloff, V.Sze, B.Ginsburg, P.Mercier, D.Daly, and R.Blazquez, ''Low-power impulse uwb architectures and circuits,'' Proc. IEEE, vol.97, no.2, pp. 332 --352, 2009.
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[^2]: A.Eftekhar, S.Paraskevopoulou, and T.Constandinou, ''Towards a next generation neural interface: Optimizing power, bandwidth and data quality,'' in Proc. IEEE BioCAS, 2010, pp. 122 --125.
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[^3]: I.Stevenson and K.Kording, ''How advances in neural recording affect data analysis,'' Nature neuroscience, vol.14, no.2, pp. 139--142, 2011.
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[^4]: T.Buchegger, G.Ossberger, A.Reisenzahn, A.Stelzer, and A.Springer, ''Pulse delay techniques for ppm impulse radio transmitters,'' in Proc. IEEE Conf. UWB Syst. Tech., 2003, pp. 37 -- 41.
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[^5]: R.Hoctor and H.Tomlinson, ''Delay-hopped transmitted-reference rf communications,'' in Proc. IEEE Conf. UWB Syst. Tech., 2002, pp. 265--269.
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[^6]: L.Moreira, W.van Noije, D.Silveira, S.Kofuji, and C.Sassaki, ''A small area 2.8pj/pulse 7th derivative gaussian pulse generator for ir-uwb,'' in Proc. CJMW, 2011, pp. 1 --4.
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[^7]: J.Liang, C.Chiau, X.Chen, and C.Parini, ''Study of a printed circular disc monopole antenna for uwb systems,'' IEEE Trans. Antennas and Propagation, vol.53, no.11, pp. 3500 -- 3504, 2005.
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[^8]: M.Mark, Y.Chen, C.Sutardja, C.Tang, S.Gowda, M.Wagner, D.Werthimer, and J.Rabaey, ''A 1mm$^3$ 2mbps 330fj/b transponder for implanted neural sensors,'' in Proc. IEEE VLSIC, 2011, pp. 168--169.
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[^9]: B.Qin, H.Chen, X.Wang, A.Wang, Y.Hao, L.Yang, and B.Zhao, ''A single-chip 33pj/pulse 5th-derivative gaussian based ir-uwb transmitter in 0.13$\mu$m cmos,'' in Proc. IEEE ISCAS, 2009, pp. 401--404.
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[^10]: Y.Park and D.Wentzloff, ''An all-digital 12pj/pulse 3.1 - 6.0ghz ir-uwb transmitter in 65nm cmos,'' in Proc. IEEE ICUWB, vol.1, 2010, pp. 1--4.
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[^11]: H.Miranda and T.Meng, ''A programmable pulse uwb transmitter with 34% energy efficiency for multichannel neuro-recording systems,'' in Proc. IEEE CICC, 2010, pp. 1--4.
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[^12]: P.Mercier, D.Daly, and A.Chandrakasan, ''An energy-efficient all-digital uwb transmitter employing dual capacitively-coupled pulse-shaping drivers,'' IEEE JSSC, vol.44, no.6, pp. 1679--1688, 2009.
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---
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title: "A Compact Recording Array for Neural Interfaces"
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date: 2013-09-13T15:26:46+01:00
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draft: false
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toc: true
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type: posts
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||||
math: true
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tags:
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- publication
|
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- instrumentation
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- CMOS
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- biomedical
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- sensor
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---
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Lieuwe B. Leene, Yan Liu, Timothy G. Constandinou
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Department of Electrical and Electronic Engineering, Imperial College London, SW7 2BT, UK
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Centre for Bio-Inspired Technology, Institute of Biomedical Engineering, Imperial College London, SW7 2AZ, UK
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# 1 Abstract
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This paper presents a 44-channel front-end neural interface for recording both Extracellular Action Potentials (EAPs) and Local Field Potentials (LFPs) with 60 dB dynamic range. With a silicon footprint of only 0.011 mm² per recording channel this allows an unprecedented order of magnitude area reduction over state-of-the-art implementations in 0.18 μm CMOS. This highly compact configuration is achievable by introducing an in-channel Sigma Delta assisted Successive Approximation Register (\\(\Sigma\Delta\\)-SAR) hybrid data converter integrated into the analogue front-end. A pipelined low complexity FIR filter is distributed across 44-channels to resolve a 10-bit PCM output. The proposed system achieves an input referred noise of 6.41 μVrms with a 6 kHz bandwidth and sampled at 12.5 kS/s, with a power consumption of 2.6 μW per channel.
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# 2 Introduction
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The recent trend in on-chip instrumentation for neural electrophysiological recording has largely been motivated by the growing interest in observing large scale neuronal activity using small chronic implants. Such tools are crucial in the quest to better understand the brain, but also in revealing fundamental mechanisms behind neurological and psychiatric diseases for developing new diagnostics and therapeutic devices. Microelectronic bio-instrumentation systems currently have the capacity for profoundly impact such key scientific efforts [^1].
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State-of-the-art neural recording systems have made significant progress over past years by objectively improving figures of merit, most notably that of the Noise Efficiency Factor (NEF) [^2]. This progress has not however generally had the same impact on silicon footprint, which is also critical for the long term increase in recording capacity and System-on-Chip (SOC) platforms. Although a number of compact circuits including analogue amplifiers and data converters have been proposed for biomedical applications, less attention has been given to area reduction from a system perspective apart from the typical multiplexing of the Analogue-to-Digital Converter (ADC). This is partly due to the challenge in multiplexing ultra low power analogue without significantly degrading performance (i.e. due to parasitics and inter-channel interference). The work presented herein applies a number of ideas aimed at collectively reducing the silicon area towards highly scalable systems. Through a combination of novel structures and circuit level implementations that allow for hardware reuse (and thus area reduction), this work demonstrates the capacity for unprecedented area efficiency at the system level.
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The target system specifications herein apply to a Brain Machine Interface (BMI) recording the (raw) signal including both LPFs and EAPs. Furthermore, such a system can provide undistorted EAP recordings which are typically due to a high pass filter centred around 100--500 Hz. This implies an input-referred signal amplitude ranging from 10 μV to 10 mV, which has a dynamic range equivalent to that of a10-bit converter with a frequency bandwidth of 100 mHz to 3 kHz for optimal data post processing [^1]. This system aims towards a robust SOC platform, utilising a fully-differential structure to reject supply noise, as well as even order distortion harmonics, for the integration of a very large number of recording channels with wireless and digital post-processing systems.
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This organisation of this paper is as follows: Section 3 outlines the proposed system-level architecture; Section 4 details the circuit level implementation; Section 9 presents simulated system and circuit level results; and finally, Section 10 compares the overall system characteristics to the current state-of-the-art and concludes the paper.
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# 3 System Architecture
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{{< figure src="/images/biocas2013/I1.png" title="Figure 1: Top level architecture of the proposed system." width="500" >}}
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The top level system is illustrated in Fig 1, showing the in-channel architecture consisting of two multiplexed low noise amplifiers, a hybrid data converter, and two ultra compact digital filters. The system integrates 44-channels together with the primary objective being to combine state-of-the-art instrumentation techniques to achieve a substantial reduction in area through a novel implementation. The Front End Amplifier (FEA) utilises a chopper technique to alleviate the need for very large transistors and a Sigma Delta assisted Successive Approximation Register (\\(\Sigma\Delta\\)-SAR) is developed to significantly reduce the size of the capacitor bank typically required for a 10-bit resolution output. This capacitor bank is also used to implement a switched-capacitor digital filter to reject the unwanted chopper harmonics thus avoiding the requirement for additional analogue filter blocks. Finally, the filter needed to decimate the \\(\Sigma\Delta\\)-SAR modulator output is shared in the digital domain through a pipeline structure that require only a low resolution accumulator, thereby mitigating the computational costs typically associated with \\(\Sigma\Delta\\) decimation.
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# 4 Circuit Implementation
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## 5 Chopper Modulated Analog Front End
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{{< figure src="/images/biocas2013/I2.png" title="Figure 2:FEA structure illustrating the feedback and chopper configuration." width="500" >}}
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The AFE is illustrated in Fig. 2. This Capacitively-Coupled Chopper Instrumentation Amplifier (CCIA) [^3] consists of a Miller compensated 2-stage design with capacitive feedback. Using a single analogue block for amplification naturally has its trade-off as the high gain requirement implies a large input capacitance C<sub>in<sub> = 6.5 pF) but at the same time reduces the value of the Miller capacitor that introduces the dominant pole of the system for a given thermal noise floor. The feedback network is configured to introduce 34 dB of differential gain and improve the input impedance of the amplifier through positive feedback where C<sub>fp<sub> = C<sub>fb<sub>, Zin=\\( \frac{Gain}{2 \cdot f_{chop} \cdot C_{in}}\\) = 77 MΩ, and f<sub>chop<sub> = 50 kHz.
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{{< figure src="/images/biocas2013/I5.png" title="Figure 3:Circuit level schematic of the FEA." width="500" >}}
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The circuit level schematic of the FEA is shown in Fig. 3. This implementation uses the complementary input pair to allow good current efficiency for the 1.8 V analogue supply together with a class-AB, low output resistance, cascade gain stage to drive the large switching capacitance loading the output from the feedback network. The circuit also includes the common mode feedback and ADC sampling capacitors. A MOS capacitor is used to introduce the dominant pole at 6 kHz while the feedback network is implemented using MIM capacitors. The overall high pass behaviour of this structure is implemented through the periodic reset of the input and the output which also auto-zeros the input pair offset. This offset compensation is maintained outside the reset phase by biasing the gate of the reset switch at the mid-rail voltage such that it behaves as a traditional MOS-based pseudo-resistor. This reset mechanism benefits due to the improved noise characteristic over a DC-servo loop implementation that also requires a significant amount of additional area. However, the signal distortion introduced though this technique can be compensated in the digital domain [^4]. All current sourcing transistors (M5-M10) have cascode implementations (not shown in Fig. 3) to provide adequate common mode rejection and common mode input range of \\(\pm\\)200 mV, which is biased and filtered through the reset switch.
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## 6 Hybrid \\(\Sigma\Delta\\) assisted SAR ADC
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The data converter is based on extending the resolution of a small 6-bit SAR ADC with a continuous time \\(\Sigma\Delta\\) modulator that resolves the remaining quantisation error residue from the SAR algorithm. The primary components of the modulator are integrated into the pre-gain stage structure of the comparator as illustrated in Fig. 4. During initial SAR operation the gm-C filter is switched out and the input pair directly feeds into a diode-connected load for wideband operation while the filter capacitors are reset. Once the last SAR bit is resolved the loop filter is enabled implementing a second-order chain of integrators with a weighted feedforward summation modulator topology that allows low power operation with minimised signal distortion. Note that in Fig. 4 during SAR operation V\\(\Sigma\Delta\\) is at the common mode and is then modulated between ±V<sub>ref<sub> such that the feedback is necessarily always twice as large as the residue error to ensure modulator stability and optimal residue quantisation.
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{{< figure src="/images/biocas2013/I3.png" title="Figure 4: Circuit level schematic of the hybrid \\(\Sigma\Delta\\)-SAR converter." width="500" >}}
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The general organisation and operation of the ADC is illustrated in Fig. 7. Given that N=6 is the resolution of the SAR DAC and OSR=44 is the conventional oversampling ratio of the modulator. It can be observed that both SAR and \\(\Sigma\Delta\\) operation is at 5 MHz and takes N+OSR cycles to finish or a total of 10 μs for a sampling rate of 25 kHz at the 25 % duty cycle. In addition to using 5 reference voltages this topology makes a extreme reduction in size by a factor of 32 and will allow large 8 by 8 μm² unit capacitors to reduce the sensitivity of process variation thereby achieving a 10-bit resolution without any in-channel calibration.
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## 7 Chopper Rejection
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In order to reject chopper harmonics introduced by the up-modulated offset aggressors, the capacitive array is used as a switched capacitor network to implement a notch filter centred around the odd harmonics of the chopper frequency when the data converter is not operational. The output of the AFE is sampled in the time domain and weighted using different sets of capacitors to implement a 3<sup>rd<sup> order Bartlett window filter before ADC conversion. This technique avoids the need for a ripple reduction loop which typically also requires an analogue filter with large capacitors. Fig. 5 shows the 4-phase sampling sequence that operates at 50 kHz. The net charge, Q<sub>total<sub>, quantised by the converter is expressed as follows.
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$$ \frac{Q_{total}}{C_{unit}} = 8 V_{diff} \left[ n-1 \right] + 16 V_{diff} \left[ n-2 \right] + 8 V_{diff} \left[ n-3 \right] $$
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Where V<sub>diff<sub> is the sampled differential output voltage of the amplifier and C<sub>unit<sub> is the 120 fF unit capacitance of the converter that also averages sampling noise during conversion. This allows the notch filter characteristic illustrated in Fig. 5, to reject a significant amount of high frequency aggressors.
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{{< figure src="/images/biocas2013/F2.png" title="Figure 5:Switched capacitor filter timing diagram (left) and frequency response (right)" width="500" >}}
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## 8 Digital Filter
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The filter structure used to process the \\(\Sigma\Delta\\) output is illustrated in Fig. 6. This structure distributes the overall structure across all channels such that each channel requires only a 7-bit register, a 12-bit registered add/subtract accumulator as well as the two 7-bit registers from the SAR to implement the hybrid functionality demonstrated here. The filter coefficients are hardwired into each channel's 7-bit register such that it is loaded during reset and circulated through all channels.
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{{< figure src="/images/biocas2013/I6.png" title="Figure 6:Implementation of the pipelined FIR structure." width="500" >}}
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The \\(\Sigma\Delta\\) output sign modulates the accumulator which integrates over a 44-point hanning window, implementing a FIR filter without multipliers. A more traditional decimation filter implemented using a cascaded integrator comb (CIC) filter is much less effective here. This is because the structures cannot be shared (across channels) and will require a larger number of samples than the OSR to evaluate the residue error which due to the intermediate SAR process being continuously disrupted. Fortunately the resolution only needs to be extended by 4-bits to achieve the required 60 dB dynamic range. Therefore a compact 44<sup>th<sup> order window at 7-bit unsigned resolution suffices. The structure has shown to make a good estimate of the stationary input to the modulator even with high levels of quantisation noise allowing us to decrease to resolution of the stored coefficients that are given by the following expression.
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$$ w[n] = C \cdot \left[ 1 - cos \left( \frac{2 \pi n}{N-1}\right) \right]^{0.7} $$
|
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|
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The coefficients, w[n], represent a modified hanning window that results in a better Differential Non-Linearity (DNL) characteristic over other FIR windows when quantised to 7-bits. Note that C=0.024, N=46, and $n \in \left[1, 2, ..., N-2 \right]$ represent the normalisation constant, effective filter order, and the non-zero coefficient index respectively.
|
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|
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{{< figure src="/images/biocas2013/example.png" title="Figure 7: Transient operation of the ADC conversion." width="500" >}}
|
||||
|
||||
{{< figure src="/images/biocas2013/os.png" title="Figure 8: Output of the analogue channel with a 19 mV peak to peak 1 kHz input." width="500" >}}
|
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|
||||
# 9 Simulation Results
|
||||
|
||||
Preliminary validation of the proposed implementation has been done through schematic level simulations in the Cadence IC 6.1.5 Design Environment using industry provided PSP models for the commercially available 6 Metal 0.18 μm CMOS technology (AMS/IBM C18A6/7SF). The entire channel has been stimulated with 19 mV peak to peak 1 kHz differential signal for full swing at the ADC input of which a single ADC conversion is illustrated in Fig. 7. The quantised output spectrum of this simulation is shown in Fig. 8 which indicates a 1.2% total harmonic distortion for a full swing output that is due to the AFE. Fig. 10 illustrates the characteristics of the FIR filter in time and frequency domain respectively. Fig. 11 presents 10.2 ENOB performance through the 0.5 LSB bounded integral and differential non-linearities of the converter. The channel level layout is shown in Fig. 12 indicating a 440 μm by 50 μm area requirement for 2 recording channels.
|
||||
|
||||
{{< figure src="/images/biocas2013/noise.png" title="Figure 9: Noise density simulated at the output of the FEA" width="500" >}}
|
||||
|
||||
{{< figure src="/images/biocas2013/F1.png" title="Figure 10: 7-bit quantised Hanning FIR filter showing frequency (top) and time (bottom) domain responses." width="500" >}}
|
||||
|
||||
{{< figure src="/images/biocas2013/F3.png" title="Figure 11: \\(\Sigma\Delta\\)SAR non-linearities showing INL (top), DNL (bottom)" width="500" >}}
|
||||
|
||||
{{< figure src="/images/biocas2013/Area2.png" title="Figure 12: Layout of 4 Channels integrated together with CMIM capacitors overlaying the 440 μm by 100 μm silicon footprint." width="500" >}}
|
||||
|
||||
# 10 Conclusion
|
||||
|
||||
The ultra compact topology presented has demonstrated the means by which the recording channel can scale down below a 0.01 mm² area while maintaining its recording fidelity and advanced spectral filtering characteristics. In addition the proposed 10 bit hybrid data converter achieves a factor of 32 reduction in area over equivalent data converters through pipelining and \\(\Sigma\Delta\\) modulation. With an input referred noise of 6.4 μVrms this system consumes 2.6 μW resulting in excellent Noise Area product of 0.007 μVrms mm². The overall system characteristics are shown in Table 1 demonstrating respectable performance particularly with respect to the order of magnitude reduction in area per channel and the 60 dB dynamic range for the given power budget.
|
||||
|
||||
Table 1: Performance per channel of Neural Recording Arrays
|
||||
|Reference | [^5] | [^6] | [^7] | [^8] | This work |
|
||||
|----|----|----|----|----|----|
|
||||
|Year | 2011 | 2012 | 2012 | 2012 | 2013 |
|
||||
|Tech. [nm] | 180 | 250 | 130 | 130 | 180 |
|
||||
|Power [μW] | 10.1 | 3.96 | 68 | 5.9 | 2.59 |
|
||||
|High Pass [Hz] | 126m | 100m | 1 | 200 | 100m |
|
||||
|Low Pass [Hz] | 12k | 17k | 10K | 6.9K | 6K |
|
||||
|Noise [μVrms] | 5.4 | 4.8 | 2.2 | 3.8 | 6.41 |
|
||||
|NEF | 4.4 | 2.9 | 4.5 | 2.16 | 2.27 |
|
||||
|Area [mm²] | 0.31 | 0.07 | 0.19 | 0.16 | 0.011 |
|
||||
|ADC Res. | 8 | 9 | 10 | 8 | 10 |
|
||||
|Sample [kS/s] | 125 | 60 | 31 | 27 | 12.5 |
|
||||
|
||||
# 11 Acknowledgment
|
||||
|
||||
This work was supported by the UK EPSRC (grants EP/I000569/1 and EP/K015060/1).
|
||||
|
||||
# Refernces:
|
||||
|
||||
[^1]: F.K. etal., ''Drug discovery: A jump-start for electroceuticals,'' Nature, vol. 496, pp. 159--161, 2013.
|
||||
[^2]: R.Rieger, Y.-Y. Pan, and J.Taylor, ''Design strategies for multi-channel low-noise recording systems,'' in Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, 2007, pp. 561--564.
|
||||
[^3]: Q.Fan, F.Sebastiano, J.Huijsing, and K.Makinwa, ''A 1.8 w 60 nv hz capacitively-coupled chopper instrumentation amplifier in 65 nm cmos for wireless sensor nodes,'' Solid-State Circuits, IEEE Journal of, vol.46, no.7, pp. 1534--1543, 2011.
|
||||
[^4]: Y.Chen, A.Basu, and M.Je, ''A digitally assisted, pseudo-resistor-less amplifier in 65nm cmos for neural recording applications,'' in Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on, 2012, pp. 366--369.
|
||||
[^5]: W.Wattanapanitch and R.Sarpeshkar, ''A low-power 32-channel digitally programmable neural recording integrated circuit,'' Biomedical Circuits and Systems, IEEE Transactions on, vol.5, no.6, pp. 592--602, 2011.
|
||||
[^6]: K.Al-Ashmouny, S.-I. Chang, and E.Yoon, ''A 4 $\mu$w/ch analog front-end module with moderate inversion and power-scalable sampling operation for 3-d neural microsystems,'' in Biomedical Circuits and Systems Conference (BioCAS), 2011 IEEE, 2011, pp. 1--4.
|
||||
[^7]: H.Gao, R.Walker, P.Nuyujukian, K.Makinwa, K.Shenoy, B.Murmann, and T.Meng, ''Hermese: A 96-channel full data rate direct neural interface in 0.13 m cmos,'' Solid-State Circuits, IEEE Journal of, vol.47, no.4, pp. 1043--1055, 2012.
|
||||
[^8]: A.Rodriguez-Perez, J.Masuch, J.Rodriguez-Rodriguez, M.Delgado-Restituto, and A.Rodriguez-Vazquez, ''A 64-channel inductively-powered neural recording sensor array,'' in Biomedical Circuits and Systems Conference (BioCAS), 2012 IEEE, 2012, pp. 228--231.
|
||||
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